Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

Natsui, Masanori; Tamakoshi, Akira; Endoh, Tetsuo; Ohno, Hideo; Hanyu, Takahiro

doi:10.7567/jjap.56.04cn01

Cited by 7 publications

(5 citation statements)

References 29 publications

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“…1,2) Emerging material systems exploiting a new degree of freedom in nanostructures have been considered to control the weights and efficiently calculate them in brain-inspired hardware. 7,8) Two approaches could be taken in a process to apply such emerging devices in new hardware; one is circuit-friendly top down 9) and the other is device-based bottom up. 7,8) In this paper, we present these two approaches, one at the circuit level and the other at the device level, which should enable the development of an efficient memristive system for continuous weight synapses for use in creating artificial neurons.…”

Section: Introductionmentioning

confidence: 99%

Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing

Marukame¹,

Nishi²,

Yasuda³

et al. 2018

Jpn. J. Appl. Phys.

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The use of memristive devices for creating artificial neurons is promising for brain-inspired computing from the viewpoints of computation architecture and learning protocol. We present an energy-efficient multiplier accumulator based on a memristive array architecture incorporating both analog and digital circuitries. The analog circuitry is used to full advantage for neural networks, as demonstrated by the spike-timingdependent plasticity (STDP) in fabricated AlO x /TiO x -based metal-oxide memristive devices. STDP protocols for controlling periodic analog resistance with long-range stability were experimentally verified using a variety of voltage amplitudes and spike timings.

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Section: Introductionmentioning

confidence: 99%

Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing

Marukame¹,

Nishi²,

Yasuda³

et al. 2018

Jpn. J. Appl. Phys.

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“…Further, thanks to the 3D integration feasibility of MTJs over CMOS at the back-end process, it reduces the area occupied on silicon and shortens the distance between memory and logic unit in SoC. There is much scope at the backend process to improve, and the intense investigation is required to fabricate more precise prototypes [28,340,352,353,354]. From a future perspective, we have highlighted hybrid CMOS/MTJ circuits, which can be further used to develop the ultra-low-power VLSI processor.…”

Section: Circuit Perspective-various Hybrid Cmos/mtjmentioning

confidence: 99%

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NVmemory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

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“…With the advancement of internet-of-things (IoT) applications, a logic large-scale integration (LSI) design technology, utilizing a nonvolatile memory (NVM) function of a magnetic tunnel junction (MTJ) device, [1][2][3][4][5] has attracted attention. [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] By embedding a nonvolatile retention function in the LSIs, a power gating technique for wasted-power reduction can be applied at low cost, making it possible to realize highly energy-efficient LSIs. The effectiveness of nonvolatile logic LSIs has been demonstrated through the design and fabrication of various dedicated and generalpurpose hardware, such as microcontroller units (MCUs) for IoT sensor node, 17,18) field-programmable gate arrays, [8][9][10]14) and ternary content addressable memories, 11) as well as elemental circuits for neural network hardware.…”

Section: Introductionmentioning

confidence: 99%

Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Natsui

Yamagishi

Hanyu

2021

Jpn. J. Appl. Phys.

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Nonvolatile flip-flop (NVFF) is an important component for implementing an energy-efficient logic large-scale integration (LSI) circuit that utilizes nonvolatile memory (NVM) function of magnetic tunnel junction (MTJ) devices. NVFF must be highly reliable in data store and restore operations for nonvolatile power gating. This study proposes an NVFF that can detect arbitrary errors occurring when storing data to the embedded NVM caused by the stochastic behavior of MTJ devices. The performance evaluation results show that the proposed NVFF can detect arbitrary error conditions, including the unsupported condition in the previously proposed reliable NVFF, while maintaining comparable performance to a conventional condition in normal flip-flop operations.

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Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

Cited by 7 publications

References 29 publications

Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing

Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

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