Extremely-low-noise CMOS Image Sensor with high saturation capacity

Itonaga, K.; Mizuta, Kyohei; Kataoka, T.; Yanagita, M.; Ikeda, H.; Ishiwata, H.; Tanaka, Yutaka; Wakano, T.; Matoba, Yoshihisa; Oishi, Toshiyuki; Yamamoto, Ryo; Arakawa, Shin’ichi; Komachi, J.; Katsumata, M.; Watanabe, S.; Saito, Suguru; Tsutomu, Haruta; Matsumoto, Shigeyuki; Ohno, Keiichi; Ezaki, Takayuki; Nagano, T.; Hirayama, Teruo

doi:10.1109/iedm.2011.6131511

Cited by 18 publications

(8 citation statements)

References 3 publications

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“…On the other hand, negative bias at the transfer gate (TG) was also proposed to accumulate holes under TG and reduce the generation current under TG [6,7]. Most recently, STI-free structure over the whole pixel area is reported for reducing dark current [5]. To remove the STI is the best effective way to reduce dark current caused by process damage of STI, but there is a drawback which requires wider electrical isolation area for the operation of in-pixel transistors.…”

Section: Introductionmentioning

confidence: 99%

A novel pixel design with hybrid type isolation scheme for low dark current in CMOS image sensor

Choi

Kim

et al. 2013

SPIE Proceedings

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New isolation scheme for CMOS image sensor pixel is proposed and its improved dark current performance is reported. It is well known that shallow trench isolation (STI) is one of major sources of dark current in imager pixel due to the existence of interfacial defects at STI/Si interface. On the account STI-free structure over the whole pixel area was previously reported for reducing dark current. As the size of pixel pitch is shrunk, however, it becomes increasingly difficult to isolate in-pixel transistors electrically without STI. In this work, we implemented hybrid type isolation scheme of removing STI around photodiode to suppress the dark current and remaining STI near transistors to guarantee the electrical isolation of transistors in pixel. It was successfully achieved that the dark current was significantly reduced by removing the STI around the photodiode together with normal operation of in-pixel transistors.

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Section: Introductionmentioning

confidence: 99%

A novel pixel design with hybrid type isolation scheme for low dark current in CMOS image sensor

Choi

Kim

et al. 2013

SPIE Proceedings

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“…However, the use of STI in CMOS image sensors brings a large surface leakage current induced by Si/SiO 2 interface states contributing to the pixel dark noise, even though the noise performance of CMOS image sensors has been greatly improved since the introduction of the pinned photodiode technology [6]. To solve this problem, an STI-less CIS recently reported [7] has a high signal-to-noise ratio (SNR) as removing the dark current generated from the interface defects that are located at the STI corners. In this technology, however, special process steps are required for pixel isolation.…”

Section: Introductionmentioning

confidence: 99%

A high fill-factor low dark leakage CMOS image sensor with shared-pixel design

et al. 2014

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We have developed and evaluated the high responsivity and low dark leakage CMOS image sensor with the ring-gate shared-pixel design. A ring-gate shared-pixel design with a high fill factor makes it possible to achieve the low-light imaging. As eliminating the shallow trench isolation in the proposed pixel, the dark leakage current is significantly decreased because one of major dark leakage sources is removed. By sharing the in-pixel transistors such as a reset transistor, a select transistor, and a source follower amplifier, each pixel has a high fill-factor of 43 % and high sensitivity of 144.6 ke -/lx·sec. In addition, the effective number of transistors per pixel is 1.75. The proposed imager achieved the relatively low dark leakage current of about 104.5 e -/s (median at 60°C), corresponding to a dark current density J dark_proposed of about 30 pA/cm 2 . In contrast, the conventional type test pixel has a large dark leakage current of 2450 e -/s (median at 60°C), corresponding to J dark_conventional of about 700 pA/cm 2 . Both pixels have a same pixel size of 7.5×7.5 μm 2 and are fabricated in same process.

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“…The addressable array structure is often used in obtaining the variability data of specific elements [2]. In particular, to construct reliable devices like the standard cell [3], CMOS imagers [4] and memory [5], all of whose layout-area limitations preclude the use of redundant elements, an array structure that can detect soft failure before shipping is needed. Various array structures to detect soft failure have already been reported [6][7].…”

Section: Introductionmentioning

confidence: 99%