A novel pixel design with hybrid type isolation scheme for low dark current in CMOS image sensor

Abstract

New isolation scheme for CMOS image sensor pixel is proposed and its improved dark current performance is reported. It is well known that shallow trench isolation (STI) is one of major sources of dark current in imager pixel due to the existence of interfacial defects at STI/Si interface. On the account STI-free structure over the whole pixel area was previously reported for reducing dark current. As the size of pixel pitch is shrunk, however, it becomes increasingly difficult to isolate in-pixel transistors electrically without STI. In this work, we implemented hybrid type isolation scheme of removing STI around photodiode to suppress the dark current and remaining STI near transistors to guarantee the electrical isolation of transistors in pixel. It was successfully achieved that the dark current was significantly reduced by removing the STI around the photodiode together with normal operation of in-pixel transistors.

Pixel Design Driven Performance Improvement in 4T CMOS Image Sensors: Dark Current Reduction and Full-Well Enhancement

“…Techniques like ring-gate shared pixel design enclosed by p-type layers, have also been proposed [10]. Choi et al have suggested a hybrid STI/p-well isolation scheme to achieve low leakage [23], which was benchmarked against the STI and the pure p-well isolation techniques. However, the pure p-well isolation was achieved with high spacing leading to low fill factor (FF) and the hybrid-p-well isolation was compared to the STI isolation by keeping a similar FF.…”