Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

Abstract

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this paper. Increased bitline (BL) resistance in sub-10nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate transistors on write margin considering the negative bitline (NBL) assist technique.

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

“…The read delay is defined as the timing from half of the clock signal to half of the data output from the sense amplifier when reaching 150 mV voltage difference between BLs. An artificial writeassist write driver voltage (VWD) [18] with a positive ramp-up slope from zero to a voltage larger than VDD is applied on BL to ensure successful write operation without specific peripheral circuits. The write margin is defined as VDD minus minimum VWD which confirms the data flip [18].…”

“…An artificial writeassist write driver voltage (VWD) [18] with a positive ramp-up slope from zero to a voltage larger than VDD is applied on BL to ensure successful write operation without specific peripheral circuits. The write margin is defined as VDD minus minimum VWD which confirms the data flip [18]. After obtaining this write margin value, it is set as a constant VWD for both write delay and write energy worst-case simulations.…”

“…On the other hand, increasing PMOS stress (stronger PG devices) improves write margin by facilitating faster charging of data storage nodes. Note that our write margin methodology uses transient simulation to capture the overall impacts of parasitic resistance, capacitance, and PG transistors (reported in [18]). Hence, the write margin is determined by the RBL, CBL, transistor's drive strength between PG and PD devices, and VSS resistance (RVSS) caused by wires and connected vias in the write path.…”

“…However, limited RBL and CBL reduction in A3 CFET SRAMs still cause poor (negative value) write margins. This implies a high risk of write failure [18], which should be solved by further write margin enhancement strategies such as BEOL optimization and supplementary DTCO in the future. The read delay between A14 NSFET and A10 FSFET SRAM is similar since the latter one has less RWL and CBL but a larger RBL.…”