Area-selective deposition (ASD) is a promising bottom-up manufacturing solution for catalysts and nanoelectronic devices. However, industrial applications are limited as highly selective ASD processes exist only for few materials. “Passivation/deposition/defect removal” cycles have been proposed to increase selectivity, but cycling requires the passivation to be selective to the growth surface as well as the ASD-grown material. Dimethylamino-trimethylsilane (DMA-TMS) can passivate SiO2 surfaces by covering them with −Si(CH3)3 groups. However, the interaction of DMA-TMS with materials other than SiO2 and Si remains largely unknown and its compatibility with cycling is not yet understood. This work investigates the selectivity of metal, nitride, and oxide atomic layer deposition (ALD) to DMA-TMS-passivated SiO2 as well as the surface chemistry and selectivity of the DMA-TMS reaction. The ALD coreagents O2, NH3, and H2O show low reactivity with the −Si(CH3)3-terminated surface at temperatures up to 300 °C, but the selectivity of ALD strongly depends on the metal precursor and temperature. We demonstrate that DMA-TMS is a selective passivation agent for ASD of and on TiO2, TiN, and Ru selective to SiO2, by TiCl4/H2O, TiCl4/NH3, and EBECHRu/O2 ALD, respectively. We investigate the DMA-TMS reaction on Ru and TiN/TiO2 growth surfaces under conditions that passivate SiO2. At least 77% of the area of the growth surface remains reactive for ALD, confirming the compatibility of DMA-TMS with cycling for ASD. We investigate the impact of changes in surface composition due to patterning before ASD and find that DMA-TMS removes F impurities on TiN and TiO2 surfaces. DMA-TMS selectively passivates SiO2 on three-dimensional (3D) nanopatterns, allowing preferential TiO2 deposition on a nonpassivated growth surface. Thus, the selectivity of DMA-TMS shows great promise to expand the ASD material space as well as to increase selectivity during ASD cycles.
The demand for transistors and memory devices with smaller feature sizes and increasingly complex architectures furthers the need for advanced thin film patterning techniques. A prepatterned, sacrificial layer can be used as a template for bottomup fill of new materials which would otherwise be difficult to pattern using traditional top-down lithographic methods. This work investigates initial growth of TiN, TiO 2 , and HfO 2 thin films during thermal atomic layer deposition (ALD) onto a high density, amorphous carbon (aC) sacrificial layer. ALD of TiN by TiCl 4 / NH 3 at 390 °C, TiO 2 by Ti(OCH 3 ) 4 /H 2 O at 250 °C, and HfO 2 by HfCl 4 /H 2 O at 300 °C on as-deposited aC films resulted in uninhibited, continuous thin film growth. We find that carbon surface reduction and passivation using a H 2 plasma resulted in delayed film coalescence for TiN, TiO 2 , and HfO 2 on the aC. After 200 TiN cycles on H 2 plasma-treated aC, Rutherford backscattering spectrometry shows Ti levels below the detection limit (8 × 10 13 at/cm 2 ), whereas SiO 2 or Si 3 N 4 substrates show TiN growth of ∼6 nm, corresponding to a selectivity of ∼200:1. Exposing plasma-treated aC to H 2 O induces nucleation for TiN ALD, consistent with favorable nucleation on hydroxyl sites. Therefore, the H 2 O co-reagent in TiO 2 and HfO 2 ALD contributes to loss of selectivity compared to TiN ALD using NH 3 . We confirm scaling of selectivity to sub-50 nm patterns using 45 nm aC/Si 3 N 4 line/space patterns, where 3.5 nm TiO 2 and 5.8 nm TiN films are deposited on Si 3 N 4 with minimal particle formation on aC, with selectivity loss primarily on feature corners and edges. We conclude that improved scaling of selectivity to nanometer scale patterns can be achieved by optimizing surface loading and extent of plasma exposure, and by further understanding shape effects in nanoscale surface plasma modification.
In this paper, we optimize the stack of a 90-nm CMOS-friendly W\Al 2 O 3 \Cu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al 2 O 3 \Cu interface make it possible, on one hand, to ensure cell integrity after back-endof-line processing at 400°C and, on the other, to obtain excellent memory performances. After optimization of the Al 2 O 3 layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (10 ns) at low voltage (<3 V), and low-current (10 µA), and multilevel operation. Finally, 10 6 cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125°C.Index Terms-Conductive bridging, conductive-bridging random access memory, electrochemical memory cell (ECM), high-performance memory, low-power memory, thermal stability.
Area-Selective Deposition (ASD) receives increasing attention as a bottom-up approach for nanoelectronic device fabrication. Uptake of ASD is however limited by defects, which manifest as undesired particle growth on the non-growth surface. We demonstrate a defect mitigation solution for Ru ASD on TiN/SiO2 nanopatterns by making use of the size-dependent Ru nanoparticle reactivity. During the initial stages of 1-(ethylbenzyl)-1,4-(ethylcyclohexadienyl)ruthenium and oxygen (EBECHRu/O2) Atomic Layer Deposition on dielectrics, Ru particles are too small to catalytically dissociate oxygen, and their growth is suppressed. This phenomenon creates an ASD process window in which particles can be completely etched while retaining the integrity of the ASD pattern on a TiN growth surface. Decreasing the ALD temperature strongly suppressed defect growth, which can be used to expand the process window for ASD. The ASD process window is confirmed by Self-Focusing Secondary Ion Mass Spectrometry (SF-SIMS) with its low limit of detection while analyzing 10 4 structures simultaneously. No defects are detected for Ru ASD on 36nm TiN/SiO2 patterns by SF-SIMS. We apply the Ru ASD process for bottom-up block patterning and obtain functional hardmask patterns on 300mm wafers. The approach followed in this work can produce defect-free ASD processes for a wide variety of applications.
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