Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes

Pei, Zhenlin; Mayahinia, Mahta; Liu, Hsiao-Hsuan; Tahoori, Mehdi B.; Catthoor, Francky; Tőkei, Zsolt; Pan, Chenyun

doi:10.1109/ted.2022.3225512

Cited by 4 publications

(1 citation statement)

References 35 publications

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“…The contact resistance includes the metal-graphene imperfect contact resistance R con and the quantum resistance R q . In SC-MLGNR, R con =100 Ωꞏμm [7], and in TC-MLGNR, it is taken as 4.3 kΩ [8]. The p.u.l.…”

Section: Contact Resistance and Other Parametersmentioning

confidence: 99%

Performance investigation of doped multi-layer graphene nanoribbon as interconnects in modern technology nodes

Wu,

Pan

2024

J. Phys.: Conf. Ser.

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In this paper, the performance of intercalation doped multilayer graphene nanoribbons (MLGNR) with modern technology nodes is meticulously investigated. An unconditionally stable FDTD method is used to analyze the transient output of the circuit. Several cases of MLGNR interconnects under different doping materials, stacking directions and contact modes have been discussed. With multiple experiments carried out, it is shown that the Li-doped MLGNR interconnect with vertical stacking orientation has the most outstanding performance, which has the least delay compared with the traditional Cu interconnect and other counterparts in 3-nm and 5-nm nodes. In summary, the Li-doped vertically stacked MLGNR is very promising for carbon nano interconnects in the next generation of integrated circuits.

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Section: Contact Resistance and Other Parametersmentioning

confidence: 99%

Performance investigation of doped multi-layer graphene nanoribbon as interconnects in modern technology nodes

Wu,

Pan

2024

J. Phys.: Conf. Ser.

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Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Pei

Mayahinia

Liu

et al. 2023

2023 24th International Symposium on Quality Electronic Design (ISQED)

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Graphene, a promising interconnect material, is considered a potential replacement for traditional Cu interconnects. In this paper, we develop an efficient interconnect technology/memory co-design framework by integrating a realistic cell library to enable a large design space exploration for various emerging interconnect technologies. Four interconnect materials and three H-tree options are benchmarked against Cu counterparts to optimize SRAM performance in terms of energy-delay product (EDP) and energy-delay-area product (EDAP). Various interconnect-and array-level design parameters are co-designed to quantify the true potential of graphene-based interconnects for optimal performance.

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CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Liu,

Schuddinck,

Pei

et al. 2023

IEEE Trans. Electron Devices

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Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes

Cited by 4 publications

References 35 publications

Performance investigation of doped multi-layer graphene nanoribbon as interconnects in modern technology nodes

Performance investigation of doped multi-layer graphene nanoribbon as interconnects in modern technology nodes

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

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