Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access

Abstract

Graphene, a promising interconnect material, is considered a potential replacement for traditional Cu interconnects. In this paper, we develop an efficient interconnect technology/memory co-design framework by integrating a realistic cell library to enable a large design space exploration for various emerging interconnect technologies. Four interconnect materials and three H-tree options are benchmarked against Cu counterparts to optimize SRAM performance in terms of energy-delay product (EDP) and energy-delay-area product (EDAP). Various interconnect-and array-level design parameters are co-designed to quantify the true potential of graphene-based interconnects for optimal performance.