Explicit evaluation of short circuit power dissipation for CMOS logic structures

Turgis, S.; Azémard, Nadine; Auvergne, D.

doi:10.1145/224081.224104

Cited by 19 publications

(4 citation statements)

References 17 publications

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“…Depending on the approximations used to model the currents and to estimate the input signal dependency, different formulae [161] [52], with varying accuracy, have been derived for the evaluation of the short circuit power. A useful formula was recently derived in [155] that shows the explicit dependence of the short circuit power dissipation on the design and performance parameters, such as transistor sizes, input and output ramp times and the load. The idea is to adopt an alternative definition of the short circuit power dissipation, through an equivalent (virtual) short circuit capacitance C SC .…”

Section: Sources Of Power Dissipationmentioning

confidence: 99%

Power minimization in IC design

Pedram

1996

ACM Trans. Des. Autom. Electron. Syst.

392

135

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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design-ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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Section: Sources Of Power Dissipationmentioning

confidence: 99%

Power minimization in IC design

Pedram

1996

ACM Trans. Des. Autom. Electron. Syst.

392

135

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“…The short circuit power dissipation is produced by the simultaneous conduction of P and N transistors during the transition of the input signal. As shown in [9,21] the ratio of input to output transition times is a good indicator of short circuit power dissipation. For ratio values comparable or lower than unity, which is the objective of buffer design, the short circuit power dissipation can be neglected.…”

Section: -Power Dissipation In Cmos Buffersmentioning

confidence: 99%

Design and selection of buffers for minimum power-delay product

Turgis

Azémard

Auvergne

Proceedings ED&TC European Design and Test Conference

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Using explicit modeling of delays we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to standard cell library in comparing implementations for different selection alternatives.

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“…In the same way thc comparison of power contributions could be easily obtained at circuit or design level if we were able to define for each power component an equivalcnt capacitance. The macro-model used in our approach is based on the cquivalent short-circuit and overshoot capacitance concept that allows us to write the internal power term in a similar way than the capacitive one through the capacitances Csc and Cov as: Psc=q tVdd2Csc and Pov=q tVdd2Cov [7]. With this definition it is then easy to compare the different power components in terms of capacitances such as:…”

Section: -Definition Of a Macro-model For The Internal Power Compomentioning

confidence: 99%

Internal power modelling and minimization in CMOS inverters

Turgis¹,

Daga²,

Portal³

et al.

Proceedings European Design and Test Conference. ED &Amp; TC 97

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We present in this paper an alternative for tlie internal (short-circuit arid overshoot) poctrer dissipation estimation of CMOS striictiires. Using n first order macro-niodelling, we consider siihicronic additionrial effects such as: input slew dependency of short-circuit curretits arid inpiit-tooutpiit coupling. Cotisiderirzg an equivalent capacitance concept we directly compare the different power conipotietits. Validutions are presented by comparing siniirkited \*allies (HSPICE level 6, foundry model 0.7pm) to calculated ones. Application to Duffer design enlightens the iiiiportance oj tlie interiial power coriiporient arid clearly .sho,i.s tliat coninioii sizing altertiutives for power arid de1li.v iizitiinii:atioti c m De considered. I-IntroductionUsual trade-offs for low power design interchange speed with power by reducing the average active capacitance necessary to propagate signals. However carefull study of power dissipation in CMOS structures gives evidence of the importance of internal components which can have higher contributions than the external capacitive one. In order for designers to effectively reduce power dissipation, an analytical but accurate power dissipation model, considering the complete contribution of power components. is needed. This model must be design oriented to allow the estimation of power consumption for evaluating power induced design alternatives or identifying the specific parts that need to be optimized for low power. Usually three terms of power are distinguished in CMOS integrated circuits.A dynamic component due to charge and discharge of the different capacitances involved in the design: Pd=q tVdd2CL, where CL includes active diffusion and interconnect capacitances .An internal component usually called the shortcircuit component, that appears when both N and P blocks are conducting resulting in a direct path from supply to ground.A static component due to leakage currents usually neglected as long as Vdd > Vtn+lV I. First term is dominant and is mostly addressed by all authors when considering design techniques for low power [ I ,2,3]. Internal transistor power dissipation can also significantly contributes to the overall dynamic dissipation tP in certain design conditions as it has been shown by some authors [4,5]. If the purcly capacitivc dynamic component can easily be estimated, thie internal one meets difficulties for an accurate evaluation in the sense that it strongly depends on the gate design 141. Many techniques have been proposed to estimate this component using simulation [ I 1,121 as well as closed form models [4,5.6,9.10 ] that accuracy depends on the considered design parameters and control signals. With thc evolution of the submicronic range, it appears further impossible to use simple Shockley MOS models to reptoduce the voltage-current characteristics of recent short-channel MOSFET's. Since CMOS circuits do not dissipate power if they are not switching, the goal 01' this paper will be to study the different internal dissipation sources due to input ...

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Explicit evaluation of short circuit power dissipation for CMOS logic structures

Cited by 19 publications

References 17 publications

Power minimization in IC design

Power minimization in IC design

Design and selection of buffers for minimum power-delay product

Internal power modelling and minimization in CMOS inverters

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