Internal power modelling and minimization in CMOS inverters

Abstract

We present in this paper an alternative for tlie internal (short-circuit arid overshoot) poctrer dissipation estimation of CMOS striictiires. Using n first order macro-niodelling, we consider siihicronic additionrial effects such as: input slew dependency of short-circuit curretits arid inpiit-tooutpiit coupling. Cotisiderirzg an equivalent capacitance concept we directly compare the different power conipotietits. Validutions are presented by comparing siniirkited \*allies (HSPICE level 6, foundry model 0.7pm) to calculated ones. Application to Duffer design enlightens the iiiiportance oj tlie interiial power coriiporient arid clearly .sho,i.s tliat coninioii sizing altertiutives for power arid de1li.v iizitiinii:atioti c m De considered. I-IntroductionUsual trade-offs for low power design interchange speed with power by reducing the average active capacitance necessary to propagate signals. However carefull study of power dissipation in CMOS structures gives evidence of the importance of internal components which can have higher contributions than the external capacitive one. In order for designers to effectively reduce power dissipation, an analytical but accurate power dissipation model, considering the complete contribution of power components. is needed. This model must be design oriented to allow the estimation of power consumption for evaluating power induced design alternatives or identifying the specific parts that need to be optimized for low power. Usually three terms of power are distinguished in CMOS integrated circuits.A dynamic component due to charge and discharge of the different capacitances involved in the design: Pd=q tVdd2CL, where CL includes active diffusion and interconnect capacitances .An internal component usually called the shortcircuit component, that appears when both N and P blocks are conducting resulting in a direct path from supply to ground.A static component due to leakage currents usually neglected as long as Vdd > Vtn+lV I. First term is dominant and is mostly addressed by all authors when considering design techniques for low power [ I ,2,3]. Internal transistor power dissipation can also significantly contributes to the overall dynamic dissipation tP in certain design conditions as it has been shown by some authors [4,5]. If the purcly capacitivc dynamic component can easily be estimated, thie internal one meets difficulties for an accurate evaluation in the sense that it strongly depends on the gate design 141. Many techniques have been proposed to estimate this component using simulation [ I 1,121 as well as closed form models [4,5.6,9.10 ] that accuracy depends on the considered design parameters and control signals. With thc evolution of the submicronic range, it appears further impossible to use simple Shockley MOS models to reptoduce the voltage-current characteristics of recent short-channel MOSFET's. Since CMOS circuits do not dissipate power if they are not switching, the goal 01' this paper will be to study the different internal dissipation sources due to input ...

Accurate static timing analysis for deep submicronic CMOS circuits

“…• The signal slopes effects, that is commutation time of input signal (Auvergne et al 1990, Dagenais et al 1992) are computed with an RC model. • The transient short circuit current during the commutation of a gate (Turgis et al 1997) is approximated to an additional load capacitance, called here the conflict capacitance.…”