Design and selection of buffers for minimum power-delay product

Abstract

Using explicit modeling of delays we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to standard cell library in comparing implementations for different selection alternatives.

A Low-Power Multi-Pin Maze Routing Methodology

“…In general, analytical solutions tend to ignore the leakage power consumption and the wire routing problem and focus on the buffer insertion only. Another major drawback in the analytical solutions is their inability to accommodate the buffer blockage since they assume the availability of all the silicon area beneath the interconnect( [5], [6] and [7]). …”

Transistor sizing and V<inf>DD</inf> scaling for low power CMOS circuits

“…At the circuit level, which is the target of this paper, power optimization is achieved by transistor sizing, supply voltage and/or threshold voltage scaling. The works in [1]- [4] attempt to optimize switching power through transistor sizing. S. Turgis et al [1] consider a chain of inverters where a tapering ratio of 4.25 is found to minimize the power dissipation.…”

“…The works in [1]- [4] attempt to optimize switching power through transistor sizing. S. Turgis et al [1] consider a chain of inverters where a tapering ratio of 4.25 is found to minimize the power dissipation. In [2] it has been proven that the input capacitances of an inverter chain are minimized when inverters bear the same fanout.…”

Power-optimal simultaneous buffer insertion/sizing and wire sizing

“…They developed a methodology to compute the repeater size and interconnect length that minimizes the total interconnect power dissipation for a given delay penalty for a uniform long line. However, these discussions for the power dissipation in the buffer insertion either ignore the leakage power [15], [16], [19], [18], or ignore both the leakage and short-circuit power [17], [18], [19], or only consider the buffer sizing for a uniform line ignoring the wire sizing [4], [16], [17], [18], [19]. Furthermore most of these discussions were algorithmic, and did not provide closed form solutions.…”

“…Lillis el al [15] presented optimal polynomial algorithms to minimize dynamic power dissipation while satisfying given timing constraints for the wire sizing/buffer insertion problems. Turgis et al [16] discussed the buffer insertion limits and the application to the buffer design to satisfy minimum power delay product constraint. Zhou and Liu [19] considered the problem of minimizing the circuit area and power dissipation subject to delay constraints by buffer sizing.…”