Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of self-heating effects

Wang, Runsheng; Zhuge, Jing; Liu, Changze; Huang, Ru; Kim, D.-W.; Park, Donggun; Wang, Yangyuan

doi:10.1109/iedm.2008.4796806

Cited by 28 publications

(14 citation statements)

References 4 publications

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“…Therefore, to be more accurate, the temperature dependent model was revised and provided in [28] in which a temperature dependence coefficient β = R SD / T is included to take account of the R SD effect. For instance, β of FinFETs in this study is reported as 0.591 /K from [29]. Based on the corrected backscattering model, the R SD -corrected B sat was found to be obviously higher than the un-corrected one.…”

Section: Results and Disscusion A Accurate Transport Parameter Extraction For Transistorsmentioning

confidence: 60%

Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes

Zhao

2019

IEEE J. Electron Devices Soc.

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FinFET and fully depleted silicon-on-insulator (FDSOI) structures could further improve transistor's performance and, however, also introduce some new problems, especially the increasingly severer self-heating effect (SHE). In this paper, by utilizing the ultra-fast sub-1 ns measurement technique, I-V characteristics of FinFETs and FDSOI devices at different switch speeds are obtained. Furthermore, dynamic SHE phenomena as well as the time-resolved channel temperature change during transistor's switch on and off are able to be experimentally observed. And, more accurate device parameters like ballistic transport efficiency are extracted by the ultra-fast measurements. Moreover, it is experimentally confirmed that several nanoseconds are required to heat up the channel of transistors by the direct electrical characterization and, therefore, in sub-10 nm devices, SHE might be alleviated under high frequency/speed operations.

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Section: Results and Disscusion A Accurate Transport Parameter Extraction For Transistorsmentioning

confidence: 60%

Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes

Zhao

2019

IEEE J. Electron Devices Soc.

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“…was reported to be equal to or larger than those in planar SOI Tr. [10]. However, comparison between NW Tr.…”

Section: Introductionmentioning

confidence: 88%

Experimental Study of Self-Heating Effects in Trigate Nanowire MOSFETs Considering Device Geometry

Ota

Saitoh

Tanaka

et al. 2012

IEEE Trans. Electron Devices

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Temperature rise by self-heating effects in nanowire (NW) transistors (NW Trs.) is systematically studied with respect to their dependence on the structural parameters. Temperature rise in NW Tr. is found to be independent of the NW size in sub-100-nm regions when compared at the same total power consumption. This is because the heat generated by the drain current is spread to the area larger than the NW channel. Dependences of temperature rise on other parameters such as gate oxide or buried oxide thickness suggest that heat dissipates mainly via source/drain or substrate not via the gate electrode.Index Terms-Self-heating effect (SHE), silicon nanowire (NW) transistor (NW Tr.), silicon on insulator (SOI).

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“…31 65 This wodc n-SNWTs(ec.) [146] 34-84 0.21-0.38 This wodc p-SNWTs(ec.) [146] 41-91 0.30-0.55 29-54 given in ref.…”

Section: -53mentioning

confidence: 98%

“…A modified experimental extraction method is given with the temperature-dependent parasitic source resistance considered. The apparent mobility of the SNWTs is also presented [146,147] .…”

Section: Gate-all-around Silicon Nanowire Devicesmentioning

confidence: 99%

“…Based on the basic extraction procedure in ref. [150], a modified experimental extraction method was put forward [146] . For quasi-1D nanowire structures connected with three-dimensional S/D reservoirs, the temperature dependence of Rs cannot be ignored like traditional devices with channel and source/drain region in similar dimensions.…”

Section: Gate-all-around Silicon Nanowire Devicesmentioning

confidence: 99%

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Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of self-heating effects

Cited by 28 publications

References 4 publications

Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes

Impact of Self-Heating Effect on Transistor Characterization and Reliability Issues in Sub-10 nm Technology Nodes

Experimental Study of Self-Heating Effects in Trigate Nanowire MOSFETs Considering Device Geometry

Challenges of 22 nm and beyond CMOS technology

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