Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Lai, Yi‐Shao; Yang, Ping-Feng; Yeh, Chang-Lin

doi:10.1016/j.microrel.2005.07.005

Cited by 169 publications

(62 citation statements)

References 5 publications

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“…For this study the test vehicle board was mounted above the drop table in a horizontal position with the components facing downward which is the most severe orientation for board deflection [11,22]. The board was supported by four standoff poles with 8 mm diameter and 12 mm height located near the board corners.…”

Section: Drop Test Methodologymentioning

confidence: 99%

Drop impact reliability of edge-bonded lead-free chip scale packages

Farris¹,

Pan²,

Liddicoat³

et al. 2009

Microelectronics Reliability

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a b s t r a c tThis paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dyepenetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.

show abstract

Section: Drop Test Methodologymentioning

confidence: 99%

Drop impact reliability of edge-bonded lead-free chip scale packages

Farris¹,

Pan²,

Liddicoat³

et al. 2009

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…For this study the test vehicle was mounted with the board in a horizontal po sition with the components facing downward, as in Figure 3.9, which is the most severe orientation for board deflection [1,19]. Four corner shoulder screws with 12 mm standoff supported the board mounted on the drop table base plate.…”

Section: Drop Test Methodologymentioning

confidence: 99%

Drop Impact Reliability Testing Lead-Free Chip Scale Packages

Farris¹

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“…[2]- [5]. The addition of micro-additives to low-silver BGA alloys can also have a significant effect on improving the drop shock performance of the packages as well [3].…”

Section: Low-silver Ball Grid Array (Bga) Assembliesmentioning

confidence: 99%

“…The addition of micro-additives to low-silver BGA alloys can also have a significant effect on improving the drop shock performance of the packages as well [3]. 5 The investigation of drop shock performance of electronics has become very important due to the popularity of handheld electronic devices [5].…”

Section: Low-silver Ball Grid Array (Bga) Assembliesmentioning

confidence: 99%

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Reliability Analysis of Low-Silver Bga Solder Joints Using Four Failure Criteria

Kimura

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Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Cited by 169 publications

References 5 publications

Drop impact reliability of edge-bonded lead-free chip scale packages

Drop impact reliability of edge-bonded lead-free chip scale packages

Drop Impact Reliability Testing Lead-Free Chip Scale Packages

Reliability Analysis of Low-Silver Bga Solder Joints Using Four Failure Criteria

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