Evaluation of Operating Margin and Switching Probability of Voltage- Controlled Magnetic Anisotropy Magnetic Tunnel Junctions

Song, Jinouk; Ahmed, Ibrahim; Zhao, Zhengyang; Zhang, Delin; Sapatnekar, Sachin S.; Wang, Jianping; Kim, Chris H.

doi:10.1109/jxcdc.2018.2880205

Cited by 22 publications

(21 citation statements)

References 41 publications

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“…iPMA has been observed in CoFeB whose thickness is less than the critical thickness ( ), while cPMA was observed in CoPt and FePd, whose crystalline anisotropy is very high [74,75]. Mathematically the effective perpendicular anisotropy field [76] is given by,…”

Section: Interpretation Of Mamentioning

confidence: 99%

“…have been reported. But among all, precessional VCMA-assisted STT has proved to be more efficient [76,152,160] in performance and energy-efficient operations.…”

Section: F Vcmamentioning

confidence: 99%

“…For the selected model, if Vapp > Vcrit (= 1.0V), the VCMA effect is observed, while for Vapp < Vcrit (= 1.0V), the STT effect is observed. Precessional VCMA, precessional VCMA-assisted STT, and thermally activated VCMA-assisted STT switching mechanisms [76,160] are discussed by simulating the VCMA-MTJ model [363]. Due to the unavailability of the VCMA-assisted SHE MTJ model, we have redrawn the results of previously reported work by Kang et al in 2016 [152].…”

Section: Appendix Amentioning

confidence: 99%

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From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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Spintronics is one of the growing research areas which has the capability to overcome the issues of static power dissipation and volatility suffered by the complementary metal-oxide-semiconductor (CMOS) industry. Magnetic tunnel junction (MTJ), one of the prominent spintronic devices, is not only used to develop the fully non-volatile-logic (NV-L) but combines magnetism and electronics to develop next-generation NVmemory (NV-M) and hybrid CMOS/MTJ circuits. To be specific towards hybrid CMOS/MTJ circuits, the fabrication of first hybrid full-adder in 2009, fabrication of MTJ based 240-tile NV-field programmable gate array (NV-FPGA) chip in 2013, fabrication of a 3000-6-input-LUTs based NV-FPGA chip in 2015, fabrication of MTJ based NV-logic-in-memory-large scale integration (NV-LIM-LSI) in 2017 and recently the fabrication of a full hybrid magnetic/CMOS System on Chip (SoC) under EU GREAT Project in 2019 has strengthened the belief and motivated the researcher to be continued in this domain. This review article aims to provide the complete design flow of hybrid CMOS/MTJ circuits developed using one of the fab compatible MTJ spintronic devices and its integration with conventional CMOS logic. The broad coverage of the article is MTJ construction, its switching mechanisms, a brief history of various compact models, reliability issues, and the concept of logic-in-memory (LIM) architecture. Finally, the article concludes with the challenges and future prospects of hybrid CMOS/MTJ circuits, which will motivate people in academia to cultivate research in this domain and industry to realize the prototype for a wide range of potential applications.

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Section: Interpretation Of Mamentioning

confidence: 99%

“…have been reported. But among all, precessional VCMA-assisted STT has proved to be more efficient [76,152,160] in performance and energy-efficient operations.…”

Section: F Vcmamentioning

confidence: 99%

Section: Appendix Amentioning

confidence: 99%

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From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

et al. 2020

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“…Therefore, a higher energy barrier will improve the nonvolatil-ity, but it also requires a higher current to flip states. In the past ten years, researchers have theoretically proposed and experimentally verified various approaches to solve these challenges such as to temporarily lower the energy barrier right before applying an STT current by using voltage-controlled magnetic anisotropy (VCMA) effect [16][17][18][19] or heating effect, to improve the nonvolatility by incoming the anisotropy fields due to the interlayer or interfacial exchange coupling between magnetic layers, [20][21][22] and to further reduce the switching current by combining STT and spin-orbit torque (SOT) in threeterminal MTJ structure. [23] For the spin-torque driven dynamical magnetization, many studies are focused on investigating the relationship among the coherence of the dynamical states in spin-torque nano-oscillators (STNOs), [9,10,24] the magnetic properties, and the layout of magnetic nanostructures with the goal of achieving the optimized characteristics of STNOs for the specific applications in radio-frequency electronics, spin wave-based devices, and neuromorphic computing.…”

Section: Introductionmentioning

confidence: 99%

Experiments and SPICE simulations of double MgO-based perpendicular magnetic tunnel junction*

Zhang

et al. 2021

Chinese Phys. B

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We investigate properties of perpendicular anisotropy magnetic tunnel junctions (pMTJs) with a stack structure MgO/CoFeB/Ta/CoFeB/MgO as the free layer (or recording layer), and obtain the necessary device parameters from the tunneling magnetoresistance (TMR) vs. field loops and current-driven magnetization switching experiments. Based on the experimental results and device parameters, we further estimate current-driven switching performance of pMTJ including switching time and power, and their dependence on perpendicular magnetic anisotropy and damping constant of the free layer by SPICE-based circuit simulations. Our results show that the pMTJ cells exhibit a less than 1 ns switching time and write energies < 1.4 pJ; meanwhile the lower perpendicular magnetic anisotropy (PMA) and damping constant can further reduce the switching time at the studied range of damping constant α < 0.1. Additionally, our results demonstrate that the pMTJs with the thermal stability factor ≃ 73 can be easily transformed into spin-torque nano-oscillators from magnetic memory as microwave sources or detectors for telecommunication devices.

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“…We also explore various material candidates for SOT-MRAM, such as heavy metals, alloys, semimetals, and topological insulators. Note that VCMA-MRAM has not been considered in this work since it requires precise pulsewidth control [18], [19], or it needs to be combined with STT [19], [20] or SOT for a deterministic magnetization switching. The parameters for each type of MRAM are chosen from the recent state-of-theart experiments, as will be discussed in Table 2.…”

Section: Introductionmentioning

confidence: 99%

Benchmarking and Optimization of Spintronic Memory Arrays

Liao

Pan

Naeemi

2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

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In this article, we present a cross-layer optimization and benchmarking of various spintronic memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbittorque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME) MRAM. Various material, device, and circuit parameters are optimized to maximize array-level READ and WRITE performances and to benchmark spintronic devices against static random access memory (SRAM). It is shown that the optimized parameters, such as magnetic tunnel junction (MTJ) oxide thickness or transistor size, are quite different for various device options. The optimal oxide thickness of VCEC-MRAM is 1.6 nm because it is a voltage-controlled device; thus, thicker oxide gives smaller READ energy-delay product (EDP), whereas, for STT-MRAM, the optimal oxide thickness is 1.3 nm to keep the WRITE voltage low while avoiding READ disturbs. In addition, we find that the co-optimization of material, device, and circuit analyses are critical because it is not enough to identify the most promising material for various device options with only materialor device-level metrics. For instance, SOT materials with the highest spin conductivity may not result in the best array-level WRITE performance because of their large resistivity and, in some cases, READ disturb issues. We also present a new design and cell layout for ME-MRAM in which the number of access transistors depends on the WRITE voltage. The benchmarking results show that SOT-MRAM can be fast and low energy but would suffer from a 25% larger cell area compared with STT-MRAM. VCEC-MRAM can be denser than STT-MRAM (2T1MTJ) and dissipate less energy but would suffer from slower READ operations because of its large oxide thickness. ME-MRAM can be fast, low energy, and dense compared with all other options. INDEX TERMS Magnetoelectric (ME), nonvolatile memory, spintronics, spin-orbit torque (SOT), spin-transfer torque (STT), voltage-controlled exchange coupling (VCEC).

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Evaluation of Operating Margin and Switching Probability of Voltage- Controlled Magnetic Anisotropy Magnetic Tunnel Junctions

Cited by 22 publications

References 41 publications

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review

Experiments and SPICE simulations of double MgO-based perpendicular magnetic tunnel junction*

Benchmarking and Optimization of Spintronic Memory Arrays

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