Benchmarking and Optimization of Spintronic Memory Arrays

Abstract

In this article, we present a cross-layer optimization and benchmarking of various spintronic memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbittorque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME) MRAM. Various material, device, and circuit parameters are optimized to maximize array-level READ and WRITE performances and to benchmark spintronic devices against static random access memory (SRAM). It is shown that the optimized parameters, such as magnetic tunnel junction (MTJ) oxide thickness or transistor size, are quite different for various device options. The optimal oxide thickness of VCEC-MRAM is 1.6 nm because it is a voltage-controlled device; thus, thicker oxide gives smaller READ energy-delay product (EDP), whereas, for STT-MRAM, the optimal oxide thickness is 1.3 nm to keep the WRITE voltage low while avoiding READ disturbs. In addition, we find that the co-optimization of material, device, and circuit analyses are critical because it is not enough to identify the most promising material for various device options with only materialor device-level metrics. For instance, SOT materials with the highest spin conductivity may not result in the best array-level WRITE performance because of their large resistivity and, in some cases, READ disturb issues. We also present a new design and cell layout for ME-MRAM in which the number of access transistors depends on the WRITE voltage. The benchmarking results show that SOT-MRAM can be fast and low energy but would suffer from a 25% larger cell area compared with STT-MRAM. VCEC-MRAM can be denser than STT-MRAM (2T1MTJ) and dissipate less energy but would suffer from slower READ operations because of its large oxide thickness. ME-MRAM can be fast, low energy, and dense compared with all other options. INDEX TERMS Magnetoelectric (ME), nonvolatile memory, spintronics, spin-orbit torque (SOT), spin-transfer torque (STT), voltage-controlled exchange coupling (VCEC).

A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

“…Scaling down memory based on charge-based storage is facing issues due to the physical limitation of the components TABLE 1: An Overview of Memory Technologies [14], [15]. used in the memory circuits.…”

High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist

“…18(b) the cell area per bit of the SOT+VCMA/STT scheme with 4 MTJs on a shared SOT channel is compared against those of other magnetic memory options. In both plots, the 14 nm technology node (F=32nm) and the layout rules described in prior benchmarking work [11], [28] are used to calculate the cell areas. Compared to the conventional 2T SOT-MRAM, ∼2x bit density can be achieved.…”

Review of Magnetic Tunnel Junctions for Stochastic Computing

“…Magnetic random access memory (MRAM) has been developed for commercial purposes in recent years [32], [33], [34], [35], [36], [37], [38]. The elementary storage component in state-of-the-art MRAM is the MTJ, which is a two-terminal nanomagnetic device consisting of several thin-film magnetic devices, which consists of several ultrathin layers forming a nanopillar.…”