Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis

Farokhnejad, Anita; Esposto, Simone; Ciofi, Ivan; Zografos, Odysseas; Weckx, Pieter; Ryckaert, Julien; Schuddinck, P.; Xiang, Yang; Tőkei, Zsolt

doi:10.1109/iitc52079.2022.9881286

Cited by 3 publications

(2 citation statements)

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“…On the other hand, reducing both RBL and CBL is crucial to write margin improvement since case 5 and 6 provide the best results. Several approaches have been reported to reduce R-C such as flying BL (which can reduce both RBL and CBL) [20], hybrid-height metal [21], airgap [21], and high aspect ratio [21] techniques. Further developments of BEOL optimization with realistic R-C interaction should be tackled in the future by following the R-C lowering instructions given in this work.…”

Section: E Sram Benchmark and Beol Optimization Guidelinementioning

confidence: 99%

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

Liu

Salahuddin

Chan

et al. 2023

IEEE Trans. Electron Devices

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This paper explores and evaluates 6-transistor static random-access memory (SRAM) bitcell design options for sequential and monolithic complementary field-effect transistors (CFET) in 5-Åm-compatible (A5) and 3-Åm-compatible (A3) technology. A5 CFET offers up to 55% and 40% SRAM bitcell area scaling due to stacked devices as compared to 14-Åmcompatible (A14) nanosheet technology and 10-Åm-compatible (A10) forksheet technology counterparts, respectively. Dielectric isolation wall (DIW) between gates is introduced in A3 CFET SRAM as a scaling booster. Replacement of gate-cuts with DIW results in up to 17% bitcell area scaling in A3 as compared to A5 CFET SRAM. Aggressive area scaling however introduces routing complexity and limits the node-to-node power and performance gain. The interconnect design guidelines are provided to overcome these challenges for power, performance, and area (PPA) enhancements of high-density (HD) SRAM.

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Section: E Sram Benchmark and Beol Optimization Guidelinementioning

confidence: 99%

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

Liu

Salahuddin

Chan

et al. 2023

IEEE Trans. Electron Devices

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“…2). [21][22][23][24] A barrierless Ru metallization scheme was used for all the constituting elements of the VHV and Mint. The reliability of such an integration scheme for Ru has been experimentally demonstrated.…”

Section: Vhv Model Descriptionmentioning

confidence: 99%

Resistance modeling of short-range connections: impact of current spreading

Tierno

Vega-Gonzalez

Esposto

et al. 2023

Jpn. J. Appl. Phys.

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We investigated the impact of current spreading on the resistance of short-range connections by performing simulations in Synopsys Sentaurus, based on a calibrated resistivity model. As a main case study, we considered vertical-horizontal-vertical (VHV) connections, a novel cell-routing architecture based on a two-level middle-of-line scheme, that has been proposed to boost the routing of four-track standard cells beyond the 2 nm technology node. We analyzed the impact of vias and line geometry on VHV link resistance and we found that low aspect ratio (AR) lines are needed to minimize the average cell resistance. We performed extensive resistance simulations of various short-range connection schemes beyond VHV links. We concluded that large AR lines are detrimental in all cases in which the link resistance is dominated by the vias. Finally, we show that ignoring current spreading can lead to a significant miscalculation of the link resistance in such scenarios.

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