Evaluation of a three-dimensional memory cube system

Bertin, Christian; Perlman, D.J.; Shanken, Stuart N.

doi:10.1109/33.273703

Cited by 15 publications

(2 citation statements)

References 2 publications

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“…A number of concepts that exceed conventional multichip module (MCM) technology are based on stacking of packaged devices and their interconnection via side-wall contacts. Since the early 90s, corresponding techniques have been applied, among others, by the companies Irvine Sensors in co-operation with IBM [3], Dense Pack (now DEPAC Technologies) and CUBIC Memory. In the framework of ESPRIT project 6490 the so-called vertical multichip-module concept MCM-V was developed by the National Microelectronic Research Center Cork (NMRC), Alcatel Espace and Thomson CSF (now Thales) [4].…”

Section: Technological Concepts For 3d System Integration A) Stackingmentioning

confidence: 99%

3D System Integration Technologies

et al. 2003

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In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called “wiring crisis”), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.

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Section: Technological Concepts For 3d System Integration A) Stackingmentioning

confidence: 99%

3D System Integration Technologies

et al. 2003

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“…However, single-chip memory packages are not able to satisfy these requirements. Three-dimensional memory (3-DM) module can be realized by stacking the substrates or the bare chips and obtain the high packaging density [2]- [5]. Bare chip stacking results in smaller modules with higher package densities than that produced by package stacking.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional memory module

Takahashi

Senba²,

Shimada³

et al. 1998

IEEE Trans. Comp., Packag., Manufact. Technol. B

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Demand has recently increased for high packaging density and memory capacity of memory modules for electronic equipment. Our new three-dimensional memory (3-DM) module [1] satisfies this demand. This module has almost the same size as single memory packages [thin small outline packages (TSOPs): 17.4 2 9.22 2 1.2 mm] currently being used, and a package density four times as large. Electrical performance is better than that of TSOP's because the length of its wires is about half that of TSOP's wires. Moreover, the cost of fabrication this module is low. This paper reports the module's characteristics and fabrication process. The design concept is that next-generation memory devices will be produced by using current mass-produced memory devices.

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