Evaluating Large System-on-Chip on Multi-FPGA Platform

Kulmala, Ari; Salminen, Erno; Hämäläinen, Timo D.

doi:10.1007/978-3-540-73625-7_20

Cited by 13 publications

(5 citation statements)

References 3 publications

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“…Many of multi-core platforms have been proposed lately [1]. Also, various multi-core processor architectures with soft-core NIOS II are presented [2]. These platforms are designed to increase GOPS efficiency for Watts.…”

Section: Related Workmentioning

confidence: 99%

FPGA multi-core processors power consumption: soft- core vs. hard-core

Ibro

Kallbaqi

2018

2018 UBT International Conference

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Actually multi-core processors designs are limited in power consumption and performance. Consequently, it is not possible to optimize further the performance without increasing power consumption. The main challenge in multi-core processors is the fact that they have heterogeneous hardware components. This article will study different technologies for implementing multi-core processors in FPGA devices. The minimum requirement to ensure low power consumption is parallelism. The purpose of this study is to highlight the latest methodologies used in terms of environment, clock signal, testing, flexibility, cost, availability and power consumption.

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Section: Related Workmentioning

confidence: 99%

FPGA multi-core processors power consumption: soft- core vs. hard-core

Ibro

Kallbaqi

2018

2018 UBT International Conference

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“…Through these results, we can choose the best number of cores to parallelize a given application. with the NIOS II softcore were also presented in [21]. These platforms are designed to raise the efficiency in terms of GOPS per Watt.…”

Section: Tested Benchmarks This Section Gives Better Insightmentioning

confidence: 99%

Multi-Softcore Architecture on FPGA

Baklouti

Abid

2014

International Journal of Reconfigurable Computing

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To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs) are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication).

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“…So it will be used here, too. Our system design was taking into account related work like bus architectures in [11], and another multiprocessor architecture with NIOS II softcores [12].…”

Section: Random Numbers In the Gca Model And Multiprocessor Archimentioning

confidence: 99%

Efficient traffic simulation using the GCA model

Schäck

Hoffmann

Heenes

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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The GCA (Global Cellular Automata) model consists of a collection of cells which change their states synchronously depending on the states of their neighbors like in the classical CA (Cellular Automata) model. In contrast to the CA model the neighbors can be freely and dynamically selected at runtime. The GCA model is applicable to a wide range of parallel algorithms. We present a mapping of the the well known Nagel-Schreckenberg algorithm for traffic simulation onto the GCA model using agents. The vehicles are considered as agents that are modeled as GCA cells with a certain state. The proposed GCA algorithm uses multiple data and link fields per cell to interconnect the relevant cells. An agent is connected to its agent in front, and an empty cell is connected to its agent behind. In the current generation t the position of an agent is already computed for the generation t+2 (one generation in advance). Thereby the agents movements and all cell updates can directly be calculated as defined by the cell rule. No searching of specific cells during the computation is necessary. The complexity is of O(N) when simulating the N cells of an GCA sequentially. Compared to an optimizedCA algorithm (with searching for agents) the GCA algorithm executes significantly faster, especially for low traffic densities and high vehicle speeds. Simulating 2048 cells and 204 agents on a multiprocessor system resulted in a speed-up (measured in clock ticks) of 14.75 for a system with 16 NIOS II processors configured on an FPGA.

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Evaluating Large System-on-Chip on Multi-FPGA Platform

Cited by 13 publications

References 3 publications

FPGA multi-core processors power consumption: soft- core vs. hard-core

FPGA multi-core processors power consumption: soft- core vs. hard-core

Multi-Softcore Architecture on FPGA

Efficient traffic simulation using the GCA model

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