Multi-Softcore Architecture on FPGA

Baklouti, Mouna; Abid, Mohamed

doi:10.1155/2014/979327

Cited by 10 publications

(6 citation statements)

References 21 publications

(22 reference statements)

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“…us, we find different architectures that are in adequacy with the different needs. We can find single processor systems whose performance is enhanced by HW accelerators (IPs) [24], or massively parallel architectures that take advantage of the large number of processors operating in perfect parallelism [25].…”

Section: Overview Of Embeddedmentioning

confidence: 99%

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Implementation of Blockchain Consensus Algorithm on Embedded Architecture

Frikha

Chaabane

Aouinti

et al. 2021

Security and Communication Networks

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The adoption of Internet of Things (IoT) technology across many applications, such as autonomous systems, communication, and healthcare, is driving the market’s growth at a positive rate. The emergence of advanced data analytics techniques such as blockchain for connected IoT devices has the potential to reduce the cost and increase in cloud platform adoption. Blockchain is a key technology for real-time IoT applications providing trust in distributed robotic systems running on embedded hardware without the need for certification authorities. There are many challenges in blockchain IoT applications such as the power consumption and the execution time. These specific constraints have to be carefully considered besides other constraints such as number of nodes and data security. In this paper, a novel approach is discussed based on hybrid HW/SW architecture and designed for Proof of Work (PoW) consensus which is the most used consensus mechanism in blockchain. The proposed architecture is validated using the Ethereum blockchain with the Keccak 256 and the field-programmable gate array (FPGA) ZedBoard development kit. This implementation shows improvement in execution time of 338% and minimizing power consumption of 255% compared to the use of Nvidia Maxwell GPUs.

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Section: Overview Of Embeddedmentioning

confidence: 99%

“…Inspired by Baklouti and Abid [25], we have set up this system to implement the PoW consensus and more specifically the part of the Keccak 256 algorithm on FPGA to do the off-chain encryption.…”

Section: The Proposed Consensus Embedded Architecturementioning

confidence: 99%

Implementation of Blockchain Consensus Algorithm on Embedded Architecture

Frikha

Chaabane

Aouinti

et al. 2021

Security and Communication Networks

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“…Meanwhile, if a project calls for both a microcontroller and FPGA, a soft-core processor can decrease the overall printed circuit board (PCB) footprint, speed up development time, and permit more flexible redesigns by implementing both on a single chip (Romeo et al, 2018). We also can mention multi-core custom soft processors which can be used in CPU-intensive DSP applications such as image processing tasks (Amiri et al, 2017), or to simply boost parallel applications by using multi-softcore architecture (Baklouti and Abid, 2014).…”

Section: Introductionmentioning

confidence: 99%

Modular transformation of embedded systems from firm-cores to soft-cores

Ali¹,

Pora²

2021

IJES

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Although there are many 8-bit IP processor cores available, only a few, such as Xilinx PicoBlaze and Lattice Mico8 firm-cores are reliable enough to be used in commercial products. One of the drawbacks is that their codes are confined to vendor-specific primitives. It is inefficient to implement a PicoBlaze processor on non-Xilinx FPGA devices. In this paper we propose a systematic approach that transforms primitive-level designs (firm-cores) to vendor independent designs (soft-cores), while modularising them during the process. This makes modification and implementation of designs on any FPGA devices possible. To demonstrate the idea, our soft-core version of PicoBlaze is implemented on a Lattice iCE40LP1k FPGA device and is shown to be fully compatible with the original PicoBlaze macro. Rigorous verification mechanisms have been employed to ensure the validity of the porting process; therefore, the quality of transformation matches the industry expectation.

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“…Meanwhile, if a project calls for both a microcontroller and FPGA, a soft-core processor can decrease the overall printed circuit board (PCB) footprint, speed development time, and permit more flexible redesigns by implementing both on a single chip [185]. We also can mention multi-core custom soft processors which can be used in CPU intensive DSP applications such as image processing tasks [186], or to simply boost parallel applications by using multi-softcore architecture [187].…”

Section: Resultsmentioning

confidence: 99%

“…To fully materialize the competitiveness of soft-core processor we can mention multi-core custom soft processors which can be used in CPU intensive DSP applications such as image processing [186], or simply boost parallel applications by using multi-softcore architecture [187].…”

Section: Resultsmentioning

confidence: 99%

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

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The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC’s inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. In this paper a novel RC architecture is proposed that keeps the decades old programming practices intact while harnessing the power of HA. The architecture uses LLVM compiler infrastructure to receive an algorithm and then outputs the equivalent machine language, it then finds the most frequent instruction pairs and generates equivalent RC circuit called “Miniature Accelerator (MA)”. The instruction pairs are dynamically removed from pipeline and MA computed result replaces them in parallel. To demonstrate the concept the Fast Fourier Transform (FFT) algorithm which is core Digital signal processing (DSP) kernel is written in C and then executed on an ARM Cortex-M0. The execution of FFT function is improved by 14.12%. The proposed adaptive processor is fully backward compatible, compilation is automated, and no modification of exiting software or established programming paradigms is required.

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Multi-Softcore Architecture on FPGA

Cited by 10 publications

References 21 publications

Implementation of Blockchain Consensus Algorithm on Embedded Architecture

Implementation of Blockchain Consensus Algorithm on Embedded Architecture

Modular transformation of embedded systems from firm-cores to soft-cores

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

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