Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing

Bounceur, Ahcène; Mir, Salvador; Simeu, Emmanuel; Rolindez, L.

doi:10.1007/s10836-007-5006-6

Cited by 41 publications

(33 citation statements)

References 1 publication

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“…The yield loss must be taken into account also. Many authors [22][23][24] suggest that, from economical point of view, the low defect level is more important than the low yield loss. It is more expensive to ship a bad circuit than to discard a good one [22].…”

Section: Model-based Test Quality Metrics Computationmentioning

confidence: 99%

“…Following the very good idea applied in [23,24,26] instances were not generated from the MC simulation of the CUT but directly from its probabilistic model. In this way a large volume of data was generated extremely fast, in comparison with the MC method.…”

Section: Investigation Of Probabilistic Featuresmentioning

confidence: 99%

“…We determine the standard uncertainty by combining variances from (46) and the sensitivity coefficients calculated for Eqs. (22) and (23). The exemplary values ofD andŶ L , calculated from a population of 10 6 instances, are presented in Figs.…”

Section: Confidence Intervalsmentioning

confidence: 99%

See 2 more Smart Citations

Self-testing of fully differential multistage circuits using common-mode excitation

Toczek

2008

Microelectronics Reliability

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Section: Model-based Test Quality Metrics Computationmentioning

confidence: 99%

Section: Investigation Of Probabilistic Featuresmentioning

confidence: 99%

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Self-testing of fully differential multistage circuits using common-mode excitation

Toczek

2008

Microelectronics Reliability

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“…In [4], it is proposed to extract the joint probability density function (PDF) of the output parameters (performances and test measures) of a CUT from an initial sample of about one thousand circuits obtained from Monte Carlo circuit simulation (e.g. Spice or Spectre simulation).…”

Section: Introduction and Previous Workmentioning

confidence: 99%

Statistical modelling of analog circuits for test metrics computation

Beznia¹,

Bounceur²,

Mir

et al. 2013

2013 8th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (Yd. Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT)from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.

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“…In the context of testing, a number of publications deal with analog and mixed-signal circuits [18][19][20][21][22][23][24][25]. For digital circuits most approaches either restrict themselves to special classes of defects [2,9] or assume given probability distributions for parameter variations and defect impacts [10,26,27].…”

Section: Introductionmentioning

confidence: 99%

Variation-Aware Fault Modeling

Hopsch

Becker

Hellebrand

et al. 2010

2010 19th IEEE Asian Test Symposium

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To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Science China Press and Springer-Verlag Berlin Heidelberg. Fraunhofer IIS/EAS, Dresden D-010169,G e r m a n y 2 University of Freiburg, Freiburg D-79110,G e r m a n y 3 University of Paderborn, Paderborn D-33098,G e r m a n y 4 University of Passau, Passau D-94023,G e r m a n y 5 University of Stuttgart, Stuttgart D-70569,G e r m a n y Received March 21, 2011; accepted June 21, 2011Abstract To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level inf...

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Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing

Cited by 41 publications

References 1 publication

Self-testing of fully differential multistage circuits using common-mode excitation

Self-testing of fully differential multistage circuits using common-mode excitation

Statistical modelling of analog circuits for test metrics computation

Variation-Aware Fault Modeling

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