Statistical modelling of analog circuits for test metrics computation

Beznia, Kamel; Bounceur, Ahcène; Mir, Salvador; Euler, Reinhardt

doi:10.1109/dtis.2013.6527772

Cited by 3 publications

(4 citation statements)

References 11 publications

(20 reference statements)

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“…All fault-free circuits that fail the threshold detection test is assumed to be part of P(YL), and all faulty circuits that pass the test is assumed to be part of P(TE). Due to this conservative approach, the test escape that correspond to the best FoM (0.953) at P(TE) = 5•10 -2 is much worse in this study than that of an optimized P(TE) = 9.09•10 -4 from [16] and P(TE) = 1.98•10 -4 from [60]. Due to the CI choice of 0.9, the yield loss that correspond to the best FoM in this study is high at P(YL) = 1.89•10 -2 compared to that of P(YL)= 9.1•10 -3 from [16] and P(YL) = 1.98• 10 -4 from [60].…”

Section: Resultsmentioning

confidence: 76%

“…In literature on specification-driven testing, probability of test escape P(TE) and yield loss P(YL) are used as a measure for determining the efficacy of a test under investigation [13], [60]. P(YL) is defined as functional CUTs that fail the test despite meeting the required performance specification, where P(TE) is defined as circuits not meeting specification that pass the tests.…”

Section: Figure Of Merit Calculationmentioning

confidence: 99%

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Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers

Nel

Dualibe

Stander

2023

IEEE Open J. Circuits Syst.

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Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FoM) across PVT variation. This is done using a 2.4 GHz LNA in 0.35 μm CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape P(TE) and yield loss P(YL) of 5•10 -2 and 1.89•10 -2 respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noisefiltered oscillating tone is found the least complex approach, with an average FoM of 0.891.

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Section: Resultsmentioning

confidence: 76%

Section: Figure Of Merit Calculationmentioning

confidence: 99%

Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers

Nel

Dualibe

Stander

2023

IEEE Open J. Circuits Syst.

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“…Section 4 will describe A Tool for Analog/RF BIST Evaluation Using Statistical Models 31:3 these density estimation techniques. From the CDF, it is possible to estimate the test metrics using a direct calculation [Beznia et al 2013b] or via the generation of a larger sample of circuit instances by sampling the CDF model [Bounceur et al 2006]. It must also be noted that an analysis of the CDF model may result in the identification of output parameters that are redundant or that do not contribute to the actual test metrics results.…”

Section: Methodological Flow For Model Selectionmentioning

confidence: 99%

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Beznia

Bounceur

Euler

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques. . 2015. A tool for analog/RF BIST evaluation using statistical models of circuit parameters.

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“…In the same purpose, some approaches have introduced the specification test compaction as described in [23] and [24] that leverages the correlation among specification tests in order to perform only a few of these tests during production and predict the values of the omitted ones to reduce test cost as well as the use of BIST techniques [25]. On the other hand, several methods based on the evaluation of test metrics are proposed in [26] and [27]. Most of them are based on the estimation of the distribution of the output parameters using a small sample of circuits generated via Monte Carlo simulation.…”

Section: Prior Workmentioning

confidence: 99%

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

et al. 2018

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Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E) and the Yield Loss (Y L) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique. Keywords Analog/RF test • SVM classification • Neural Network classification • BIST evaluation 1 Introduction The test is a very important notion in the field of the validation step of analog circuit design. It is the way to confirm whether a circuit under test (CUT) satisfies all functional specifications that represent its performance parameters. Since there are no manufactured circuits at the design stage, test errors can only be

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Statistical modelling of analog circuits for test metrics computation

Cited by 3 publications

References 11 publications

Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers

Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

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