Estimating architectural resources and performance for high-level synthesis applications

Sharma, Alok; Jain, Rajiv

doi:10.1145/157485.164929

Cited by 33 publications

(45 citation statements)

References 28 publications

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“…For the time constrained scheduling problem, we show how to generate the tightest possible bounds that can be derived by ignoring the precedence constraints by solving a linear programming formulation. These bounds are therefore guaranteed to be tighter than the bounds generated by the techniques of Fernandez-Bussell [2] or Sharma-Jain [12]. As a result, we show that the linear relaxation of the ILP formulation of the time constrained scheduling problem produces tighter bounds than the two techniques mentioned above.…”

Section: Introductionmentioning

confidence: 74%

“…They also show that the techniques in [2,9,10,12] generate the same bounds; we will refer to these collectively as FernandezBussell techniques. In this section we showed that LP relaxation is tighter than Fernandez-Bussell [2] and Sharma-Jain [12]; our approach was to cast the TCS bounding problem (SIRD) solved by [2,12] as an LP instance and then show that the ceiling of the optimal solution to this LP instance is indeed optimal for the TCS bounding problem (SIRD). Both Walker and Chaudhuri [1] and Gebotys and Elmasry [3] have observed that LP relaxation found the exact bounds in all of their benchmark examples.…”

Section: Discussionmentioning

confidence: 93%

“…Chaudhuri and Walker [1] show that their technique generates tighter bounds than those produced by techniques in [2,9,10,12]. They also show that the techniques in [2,9,10,12] generate the same bounds; we will refer to these collectively as FernandezBussell techniques.…”

Section: Discussionmentioning

confidence: 96%

“…We will show how the optimal solution can be calculated in the absence of resource constraints using an LP formulation. Then, we show that these bounds are no worse than bounds due to [2] and [12] and therefore that the LP relaxation of an ILP formulation of the TCS problem produces tighter bounds than bounds due to [2,12].…”

Section: Bounds On Time-constrained Scheduling (Tcs)mentioning

confidence: 87%

“…Rim and Jain [11] and Langevin and Cerny [6] have shown algorithms for computing lower bounds for the Resource-Constrained Scheduling problem. Several authors [5,9,10,12] have shown different algorithms that compute lower bounds for both these problems or for related problems. However, in most cases, it is difficult to guarantee that any one of these techniques will always produce a tighter bound than the others, and all comparisons between these algorithms so far have been experimental in nature.…”

Section: Introductionmentioning

confidence: 99%

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On lower bounds for scheduling problems in high-level synthesis

Narasimhan

Ramanujam

2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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This paper presents new results on lower bounds for the scheduling problem in high-level synthesis. While several techniques exist for lower bound estimation, comparisons among the techniques have been experimental with few guarantees on the quality of the bounds. In this paper, we present new bounds and a theoretical comparison of these with existing bounds. For the resourceconstrained scheduling problem, we present a new algorithm which generalizes the bounding techniques of Langevin and Cerny [6] and Rim and Jain [11]. This algorithm is shown to produce bounds that are provably tighter than other existing techniques. For the time constrained scheduling problem, we show how to generate the tightest possible bounds that can be derived by ignoring the precedence constraints by solving a linear programming formulation. These bounds are therefore guaranteed to be tighter than the bounds generated by the techniques of Fernandez-Bussell [2] or Sharma-Jain [12]. As a result, we show that the linear relaxation of the ILP formulation of the time constrained scheduling problem produces tighter bounds than the two techniques mentioned above.

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Section: Introductionmentioning

confidence: 74%

Section: Discussionmentioning

confidence: 93%

Section: Discussionmentioning

confidence: 96%

Section: Bounds On Time-constrained Scheduling (Tcs)mentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

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On lower bounds for scheduling problems in high-level synthesis

Narasimhan

Ramanujam

2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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Design and implementation of synthesis prediction in RTL design

Noji

Shimizu

Hamada

et al. 1996

Systems & Computers in Japan

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SUMMARYConsideration is given to predicting the realizability of the logic synthesis and the circuit scale after the logic synthesis at the stage of the functional design before the logic synthesis. If this is realized, the manual re-design part, as well as the execution time for logic synthesis can greatly be reduced, which is a problem at the present logic synthesis. This paper considers the stage of HDL description (functional description) at the register transfer level (RTL) before the logic synthesis based on the hardware description language (HDL). It presents a method of synthesis prediction, which can predict the realizability of the logic circuit expected after the logic synthesis. In the proposed synthesis prediction, the expertiseof the HDL description for the logic synthesis integrated into the knowledge in the database and the following functions are provided.The synthesis possibility function determines the realizabilityof the logic synthesis using the constructed synthesis template. The guidance function transforms interactively the HDL description, for which the logic synthesis is decided as unrealizable, into the logic synthesis description for which the logic synthesis is possible. The predictive estimation function estimates the circuit scale (in terms of the number of logic gates) after the logic synthesis.The proposed synthesis prediction methodology is applied to the HDL macrogeneration system. It is seen that the logic circuit as intended by the designer is obtained by the logic synthesis, and the predicted number of logic gates agreed with that of the circuit after the logic synthesis within 2 10 percent, in terms of the median value. The proposed synthesis prediction can be executedwith more than 100 times higher speed compared to the actual logic synthesis execution time.

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Resource-constrained loop list scheduler for DSP algorithms

Wang

Parhi

1995

Journal of VLSI Signal Processing

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Estimating architectural resources and performance for high-level synthesis applications

Cited by 33 publications

References 28 publications

On lower bounds for scheduling problems in high-level synthesis

On lower bounds for scheduling problems in high-level synthesis

Design and implementation of synthesis prediction in RTL design

Resource-constrained loop list scheduler for DSP algorithms

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