Design and implementation of synthesis prediction in RTL design

Abstract

SUMMARYConsideration is given to predicting the realizability of the logic synthesis and the circuit scale after the logic synthesis at the stage of the functional design before the logic synthesis. If this is realized, the manual re-design part, as well as the execution time for logic synthesis can greatly be reduced, which is a problem at the present logic synthesis. This paper considers the stage of HDL description (functional description) at the register transfer level (RTL) before the logic synthesis based on the hardware description language (HDL). It presents a method of synthesis prediction, which can predict the realizability of the logic circuit expected after the logic synthesis. In the proposed synthesis prediction, the expertiseof the HDL description for the logic synthesis integrated into the knowledge in the database and the following functions are provided.The synthesis possibility function determines the realizabilityof the logic synthesis using the constructed synthesis template. The guidance function transforms interactively the HDL description, for which the logic synthesis is decided as unrealizable, into the logic synthesis description for which the logic synthesis is possible. The predictive estimation function estimates the circuit scale (in terms of the number of logic gates) after the logic synthesis.The proposed synthesis prediction methodology is applied to the HDL macrogeneration system. It is seen that the logic circuit as intended by the designer is obtained by the logic synthesis, and the predicted number of logic gates agreed with that of the circuit after the logic synthesis within 2 10 percent, in terms of the median value. The proposed synthesis prediction can be executedwith more than 100 times higher speed compared to the actual logic synthesis execution time.