The VCore [1](*) based design methodology, which has been developed at the VCDS (**) Project, is a SoC design methodology using VCores. A VCore is a reusable, high level abstracted design component. We have developed the VCore based design methodology and the VCDS tool prototype. We used the developed tool and did a trial SoC design. The design result showed that SoC design productivity improved using the proposed methodology.
In this paper, we propose a novel architecture synthesis method for SoC using VCores. VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.
The reuse of high-level design intellectual properties is indispensable to reduce SoC ciesign time. It has been difficult for SoC designers to design and coinpare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Wrtnal Cores (VCores) to perfonn architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os. etc.. and makes tradeoffs behveen lardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of the proposed method from the results of an architecture level design experiment.
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