Resource-constrained loop list scheduler for DSP algorithms

Wang, Ching Yi; Parhi, Keshab K.

doi:10.1007/bf02106824

Cited by 19 publications

(13 citation statements)

References 35 publications

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“…Table 3 shows these results. With a small number of iterations (11,15,16) we can obtain an optimal scheduling. Of course, these results dependent on the quality of the initial individuals (in our case, we have guaranteed not to have an optimal solution in the initial population).…”

Section: Test Of the Optimal Schedulingmentioning

confidence: 99%

Data dependent loop scheduling based on genetic algorithms for distributed and shared memory systems

Aguilar

Leiss

2004

Journal of Parallel and Distributed Computing

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Section: Test Of the Optimal Schedulingmentioning

confidence: 99%

Data dependent loop scheduling based on genetic algorithms for distributed and shared memory systems

Aguilar

Leiss

2004

Journal of Parallel and Distributed Computing

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“…The ordering in which these transformations are used is also important if the transformations are used in a sequential manner [26]. For example, the MARS system [32]- [33] (like most systems) requires unfolding prior to scheduling and allocation and the scheduler can perform retiming and pipelining in an implicit manner. In contrast, the integer linear programming scheduler in [56] performs unfolding and retiming and/or pipelining in an implicit way simultaneously.…”

Section: Use Of Transformations In Synthesis Systemsmentioning

confidence: 99%

“…Pipelining has been addressed in many different contexts such as architecture design [7]- [10], high-level hardware synthesis [11]- [33], compiler design [34]- [39], and in high-performance circuit design [40]- [42]. The theory of pipelining has been well addressed in the architecture design text books (see [7]- [10]) and in high-level synthesis research [21].…”

Section: Pipeliningmentioning

confidence: 99%

High-level algorithm and architecture transformations for DSP synthesis

Parhi

1995

Journal of VLSI Signal Processing

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Abstract.This survey paper reviews numerous high-level transformation techniques which can be applied at the algorithm or the architecture level to improve the performance of digital signal and image processing architectures and circuits implemented using VLSI technology. Successful design of VLSI signal and image processors requires careful selection of algorithms, architectures, implementation styles, and synthesis techniques. High-level transformations can play an important role in reducing silicon area or power at the same speed or in increasing the speed for same area. These transformations can also increase the suitability of an algorithm for a particular architectural style. The transformation techniques reviewed in this paper include pipelining, parallel processing, retiming, unfolding, folding, look-ahead, relaxed look-ahead, associativity, distributivity, and reduction in strength.

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“…On the other hand, precedence relations from node computations to data format conversions and from data format conversions to node computations should be satisfied only when data format converters are used. Therefore we need three kinds of precedence constraints: from processor to processor (10), from processor to converter (11), and from converter to processor (12)…”

Section: Ilp Model For Automatic Module Selection and Data Format mentioning

confidence: 99%

“…To further exploit the potential parallelism among iterations, schedulers have been developed which overlap multiple iterations [7], [10], [11], [19], [39]. These schedulers schedule a single iteration of the DFG but allow subsequent iterations to overlap the first.…”

Section: Blocked Schedulesmentioning

confidence: 99%

ILP-based cost-optimal DSP synthesis with module selection and data format conversion

Ito

Lucke

Parhi

1998

IEEE Trans. VLSI Syst.

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In high-level synthesis, a data flow graph (DFG) description of an algorithm is mapped onto a register transfer level description of an architecture. Each node of the DFG is scheduled to a specific time and allocated to a processor. In this paper, we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with automatic retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a processor optimal schedule. During module selection an appropriate processor is chosen from a library of processors to construct a cost optimal architecture. Furthermore, we also include the cost and latency of data format conversions between processors of different implementation styles. We also present a new formulation for minimizing the unfolding factor of the blocked schedule. The approach presented in this paper is the only systematic approach proposed so far to include implicit unfolding and to perform synthesis using nonuniform processor styles and data format converters.

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Resource-constrained loop list scheduler for DSP algorithms

Cited by 19 publications

References 35 publications

Data dependent loop scheduling based on genetic algorithms for distributed and shared memory systems

Data dependent loop scheduling based on genetic algorithms for distributed and shared memory systems

High-level algorithm and architecture transformations for DSP synthesis

ILP-based cost-optimal DSP synthesis with module selection and data format conversion

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