Error-correcting schemes with dynamic thresholds in nonvolatile memories

Abstract

Abstract-Predetermined fixed thresholds are commonly used in nonvolatile memories for reading binary sequences, but they usually result in significant asymmetric errors after a long duration, due to voltage or resistance drift. This motivates us to construct error-correcting schemes with dynamic reading thresholds, so that the asymmetric component of errors are minimized. In this paper, we discuss how to select dynamic reading thresholds without knowing cell level distributions, and present several error-correcting schemes. Analysis based on Gaussian noise models reveals that bit error probabilities can be significantly reduced by using dynamic thresholds instead of fixed thresholds, hence leading to a higher information rate.

Constructions for constant-weight ICI-free codes

“…Dynamic read thresholds have been proposed in [10] to remedy the errors caused by voltage drift. Under the assumption that all cells leak charge at the same rate, the relative levels of the cells remain unchanged.…”

Reliability and hardware implementation of rank modulation flash memory

“…In the conventional flash, data stored in a cell will be faulty when Vth crosses the read threshold, usually set at the middle of the two distributions. Several schemes using dynamically adjusted read threshold have been proposed [7][8][9] for reducing read errors. But for RM, data will not be noisy as long as the relative order with the lower ranked cells is maintained.…”

Verify level control criteria for multi-level cell flash memories and their applications

“…D i,i+1 is the optimal decision level between S i and S i+1 , which satisfies the condition of [22][23][24]. In addition, σ i,0 and σ i,1 are used separately for convenience although…”

“…Figure 3 illustrates the condition of (16) f i+1 D i,i+1 which corresponds to the definition of the optimal decision level [22][23][24]. If variances for all states are equal (i.e.,…”

“…Once ECC parameters such as n and t are selected, the WER is a function of only p. Though errors in flash memories are generally not symmetric, the asymmetric component of errors could be minimized if the decision level are selected appropriately [22][23][24]. For example, for 2-bit/cell flash memories, the errors of page 1 will be symmetric if we select the decision level D 1,2 between S 1 and S 2 which makes Q In the case of σ i = σ i+1 , the decision level D i,i+1 which makes the errors symmetric is equal to the optimal decision level D i,i+1 as follows.…”