Epitaxial Growth of Indium Arsenide Nanowires on Silicon Using Nucleation Templates Formed by Self‐Assembled Organic Coatings

Abstract

The material properties of III-V semiconductors are in many ways superior to those of Si. Examples of these properties are the possibilities for high electron mobilities and the direct bandgap in most III-V semiconductors. Even so, Si remains the standard material in the electronics industry. A successful combination of these two material systems would add new functionality and increased performance compared to standard Si technology.[1] Although these advantages have long been recognized, the monolithic integration of devicequality III-V materials on Si remains a major challenge. In this work, we report on heteroepitaxial growth of InAs nanowires (NWs) directly on Si substrates by employing self-assembled organic coatings to create an oxide template that guides NW nucleation. Such a template resembles the growth masks used in selective-area epitaxy of nanostructures on III-V substrates. [2][3][4] Importantly, Au, which is commonly used for NW synthesis but not compatible with modern complementary metal oxide semiconductor (CMOS) processing, is avoided. The described nucleation method presents clear advantages in terms of epitaxial quality and control of NW size and density distributions compared to previous results achieved on Si using catalyst-free NW growth. The control demonstrated in the fields of self-assembled [5] and printed organic nanostructures [6,7] illustrates how the method may be extended to more complex patterning in future work. NWs have been the subject of much study and have great potential as a future technology platform. [8,9] One unique feature of the NW geometry is the small NW/substrate interface, which could provide a path to monolithic integration of highperformance materials, such as heterostructure III-V device structures, onto the mainstream Si platform. The small interface helps to mitigate antiphase domain formation, and accommodates a considerable mismatch in lattice constants (ca. 12 % for InAs on Si) and thermal expansion coefficients. [10][11][12] InAs has been used in a number of NW devices (see the literature for examples [13][14][15][16] ), and is one of the most promising materials for high-speed electronics [17] due to its high electron mobility, high electron saturation velocity, and low resistance contacts; still, it has proven difficult to combine InAs directly with Si. At the same time there is a strong drive from the electronics industry to integrate high-performance nanomaterials with Si [1] using methods compatible with existing Si processing. Contamination from the commonly used Au particles in the vapor-liquid-solid (VLS) mechanism [18] for NW growth is a concern because Au is an impurity in Si, which traps electrons and holes by deep-level recombination centers. [19] Inevitably, some traces of Au will contaminate process equipment or end up in the nanostructures grown. [20,21] For this reason, Au is not compatible with modern CMOS processing. NW growth without foreign metal catalyst particles thus offers an attractive alternative to the VLS method. Approaches such...

Surface structure and morphology of InAs(111)B with/without gold nanoparticles annealed under arsenic or atomic hydrogen flux

“…3A, results in so dense islands that even in rather thin wires multiple stacking faults could be common on individual surface planes through the wire. This is of course especially relevant as InAs nanowires grown at 600°C without an Au seed particle exists [37], but show no particular occurrence of radial stacking faults. So why does this generally not occur in nanowires?…”

InAs nanowire growth on oxide-masked 〈111〉 silicon

“…For the III/V materials to supplement CMOS technology, they have to be integrated on a Si platform. Various techniques were developed to achieve this, using conventional technologies [1] as well as using nanowires [2][3][4][5][6][7], where the small lateral dimensions allow for more efficient strain relaxation thereby reducing defect formation at the interface [8,9]. InAs nanowires have been a popular candidate for this purpose; with its very large electron mobility it is a potential material for high-speed electronics [10] on Si.…”

InAs nanowire metal-oxide-semiconductor capacitors

“…1,2 NWs allow the integration of semiconductor materials with reduced lattice-matching constraints 3,4 and offer the intriguing possibility of growing III-V structures on Si substrates, thus introducing high-mobility and optically active elements on a Si platform. 5 However, many of the key parameters of the NWs such as doping level and carrier distribution are still difficult to determine in a direct and conclusive way. For conventional FETs it is possible to take advantage of capacitancevoltage ͑CV͒ characterizations to determine, in a precise way, carrier concentration and interface properties of planar metal-oxide-semiconductor ͑MOS͒ stacks.…”