Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium

Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge0.97Sn0.03 P-MOSFETs with Si2H6 Passivation and HfO2 High-k and TaN Metal Gate

“…To improve CMOS device performance, extensive research on high mobility materials has been done. For P-MOSFETs, strained SiGe (sSiGe), strained Si (sSi), Ge, InAs, InGaSb, and strained Ge (sGe) were investigated [1][2][3][4][5][6][7][8][9][10][11][12][13]. Recently, high quality germanium-tin (GeSn) alloys have also been successfully grown using low temperature CVD [12] and MBE [1], [13].…”

3D Simulation of Heavy-Ion Induced Charge Collection in Sub-100nm MOS-FETs Using Strained Silicon-Germanium

“…The active regions of device is composed of a 10 nm Si buffer layer, a 10nm strained-Si 0.76 Ge 0.24 channel layer, and a top-most 5 nm Si cap layer. For x=0.24, the critical thickness of the SiGe film is 10 nm [1]. The device is designed in this way so that the strained SiGe layer is thick enough to contain most of the inversion charge in the PMOSFETs, but not thicker than the critical thickness above which the SiGe layer is metastable [1].…”

“…For x=0.24, the critical thickness of the SiGe film is 10 nm [1]. The device is designed in this way so that the strained SiGe layer is thick enough to contain most of the inversion charge in the PMOSFETs, but not thicker than the critical thickness above which the SiGe layer is metastable [1]. The thicknesses of the gate oxide and the poly Si are 18nm and 150nm, respectively.…”

“…As the feature size enter deep micron region, a series of problem appeared to restrain the further improvement of device performance, especially for the degeneration of carrier [1,2]. Strain engineering, which has shown great promise for the continual improvement of transistor drive current and speed performance [3,4], is regarded as an important method to extend the Moore Law [5].…”

Dislocation scatterings in p-type Si1−xGexunder weak electric field

“…This strategy is capable of alleviating the two problems, instead of losing the high hole mobility advantage of pure Ge. Another merit of using a Si 1−x Ge x layer is that it can be used for both n-and p-type materials by doping appropriate impurities [21,23]. However, introducing a Si 1−x Ge x layer, even if accepting a decrease in carrier mobility, can only be used to mitigate the two problems, not fully resolve them.…”