Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge0.97Sn0.03 P-MOSFETs with Si2H6 Passivation and HfO2 High-k and TaN Metal Gate

Gong, Xiao; Su, Shaojian; Liu, Bin; Wang, Lanxiang; Wang, Wei; Yang, Yue; Cheng, Ran; Kong, Eugene Y.-J.; Cheng, Bingying; Han, Genquan; Yeo, Yee-Chia

doi:10.1149/05009.0949ecst

Cited by 6 publications

(4 citation statements)

References 16 publications

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“…11. Re-plotted NBTI data published by IBM [7] for SiGe pMOSFETs and by NUS [37] for GeSn pMOSFETs with SiO 2 /HfO 2 dielectric stack compare well with the data shown already in Fig. 5(c) for SiGe devices with reduced Si cap thickness.…”

Section: Process-and Architecture-independent Resultssupporting

confidence: 84%

“…The IBM SiGe channel 32 nm technology [7] well compares with the IMEC planar SiGe channel with reduced Si cap thickness (Note: IBM data were rescaled from a failure criterion of ΔV th = 50 mV to our failure criterion of ΔV th = 30 mV to allow cross-comparison). NUS GeSn devices [37] also show similar Vop, which well compares with IMEC relaxed-Ge. Further reliability improvement is obtained in strained-Ge channel devices [39], thanks to additional valence band offset [40].…”

Section: Process-and Architecture-independent Resultssupporting

confidence: 57%

“…Si devices can be found in the data recently published by IBM for SiGe channel pMOSFET [7] and by the National University of Singapore (NUS) for GeSn channel pMOSFETs [37] (Fig. 11).…”

Section: Process-and Architecture-independent Resultsmentioning

confidence: 97%

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NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Franco

Kaczer

Mitard

et al. 2013

IEEE Trans. Device Mater. Relib.

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Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a SiO 2 /HfO 2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups.

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Section: Process-and Architecture-independent Resultssupporting

confidence: 84%

Section: Process-and Architecture-independent Resultssupporting

confidence: 57%

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NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Franco

Kaczer

Mitard

et al. 2013

IEEE Trans. Device Mater. Relib.

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“…This model readily explains (c) the reduced NBTI and the stronger voltage-dependence in SiGe pMOS with thin Si cap. Note: the key voltage-dependence signature is observed also in SiGe data by IBM [8] and GeSn data by NUS [9] with similar gate stacks. [11].…”

Section: Superior Nbti Of Sige Pmosmentioning

confidence: 54%

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Franco

Kaczer

Roussel

et al. 2014

2014 IEEE International Integrated Reliability Workshop Final Report (IIRW)

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We present a review of our recent studies of BTI in FET devices fabricated in different material systems, highlighting the reliability opportunities and challenges of each device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies when a Si cap is used to passivate the channel and to fabricate a standard SiO2/HfO2 gate stack. We ascribe this superior reliability to a reduced interaction of channel holes with oxide defects, thanks to a favorable energy alignment of the (Si)Ge Fermi level to the dielectric stack. We discuss gate stack optimization (Ge fraction, quantum well and Si cap thicknesses, channel strain engineering) for maximum BTI reliability, and we propose a simple model able to reproduce all the experimental trends. We then invoke the model to understand the excessive BTI in other high-mobility channel gate stacks, as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability.

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NBTI in (Si)Ge Channel Devices

Franco¹,

Kaczer²

2013

Bias Temperature Instability for Devices and Circuits

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Fabrication and Negative Bias Temperature Instability (NBTI) Study on Ge_0.97Sn_0.03 P-MOSFETs with Si₂H₆ Passivation and HfO₂ High-k and TaN Metal Gate

Cited by 6 publications

References 16 publications

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

NBTI in (Si)Ge Channel Devices

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