Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Kazi, Ibrahim; Meinerzhagen, Pascal; Gaillardon, Pierre-Emmanuel; Sacchetto, Davide; Leblebici, Yusuf; Burg, Andreas; Micheli, Giovanni De

doi:10.1109/tcsi.2014.2334891

Cited by 61 publications

(39 citation statements)

References 19 publications

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“…In this work, we replace the scan-chain SRAMs (Fig. 5-a) in LUTs with NV scan-chain SRAMs borrowed from previous work [14]. The multiplexers in LUTs are still implemented by transmission gates to avoid endurance limitations of the RRAMs.…”

Section: B Rram-based Fpgas: Our Visionmentioning

confidence: 99%

“…For this purpose, we consider a conventional master-slave flip-flop realized in CMOS technology and we enhance it with non-volatile storage [14]. The non-volatile data storage is realized thanks to two RRAM devices inserted in the sink of the cross-coupled inverter pair in the slave latch.…”

Section: A Rram-based Non-volatile Flip-flopmentioning

confidence: 99%

“…Restoring the information consists in pre-charging and equalizing the nodes of the latch to V dd and then starting the race condition that depends on the discharge of the internal nodes in the RRAM branches. For more details about the flipflop architecture and principles, we refer the reader to [14] for more details.…”

Section: A Rram-based Non-volatile Flip-flopmentioning

confidence: 99%

“…Applying circuit-level optimizations improves the robustness of the cell in both regular operations and in the near/sub-V t regimes. As shown in [14], such structure is capable of tolerating variations in both CMOS and RRAM devices up to a 10% standard deviation from the nominal value of the parameters down to a very aggressive sub-V t power supply of 0.4V.…”

Section: B Near-v T / Sub-v T Optimizations and Robustnessmentioning

confidence: 99%

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A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Gaillardon

Tang

Sandrini

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Field Programmable Gate Arrays (FPGAs) rely heavily on complex routing architectures. The routing structures use programmable switches and account for a significant share in the total area, delay and power consumption numbers. With the ability of being monolithically integrated with CMOS chips, Resistive Random Access Memories (RRAMs) enable highperformance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs as well as the improved tolerance to power supply reduction, RRAM-based routing multiplexers can be used to significantly reduce the power consumption of FPGA systems with no performance compromises. By evaluating the opportunities of ultra-low-power RRAM-based FPGAs at the system level, we see an improvement of 12%, 26% and 81% in area, delay and power consumption at a mature technology node.

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Section: B Rram-based Fpgas: Our Visionmentioning

confidence: 99%

Section: A Rram-based Non-volatile Flip-flopmentioning

confidence: 99%

Section: A Rram-based Non-volatile Flip-flopmentioning

confidence: 99%

Section: B Near-v T / Sub-v T Optimizations and Robustnessmentioning

confidence: 99%

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A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Gaillardon

Tang

Sandrini

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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“…In our vision of an RRAM-based FPGA, the scan-chain SRAMs of LUTs are replaced with a non-volatile version [15], while the SRAMs along with transmission-gates in programmable routing architectures evolve to RRAMs with programming schemes. When programmed into LRS, the RRAMs propagate the signals through the datapath and achieve a similar functionality as transmission-gates in on state.…”

Section: B Rram-based Fpga Architecturementioning

confidence: 99%

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

Tang

Gaillardon

Micheli

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-Vt SRAM-based FPGA, respectively.

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Memory Applications for the Intelligent Internet of Things

2018

Memories for the Intelligent Internet of Things

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Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Cited by 61 publications

References 19 publications

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

Memory Applications for the Intelligent Internet of Things

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