Accurate power analysis for near-V&lt;inf&gt;t&lt;/inf&gt; RRAM-based FPGA

Tang, Xianglu; Gaillardon, Pierre-Emmanuel; Micheli, Giovanni De

doi:10.1109/fpl.2015.7293982

Cited by 5 publications

(2 citation statements)

References 14 publications

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“…However, FPGA-SPICE can save the manual efforts and reduce the expertise required in developing analytical models for different technologies, thanks to its generalpurpose simulation-based approach. More than the showcased examples in Section VI, FPGA-SPICE can go beyond the capability of current FPGA architecture evaluation tools by: 1) providing a baseline for examining the accuracy of analytical models; 2) prototyping FPGAs and verifying functionality [14], [15], [19]; 3) validating the effectiveness of EDA algorithms and novel FPGA architecture with post-P&R analysis [18], [19]; and 4) identifying physical design challenges in FPGAs, such as analyzing hotspot management [16], [17], and so on. The accuracy and runtime tradeoff of FPGA-SPICE can be further mitigated by exploiting hardware acceleration platforms such as multithreading, GPU, and FPGA [51]- [54].…”

Section: Discussionmentioning

confidence: 99%

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Tang

Giacomin

Micheli

et al. 2019

IEEE Trans. VLSI Syst.

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In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, gridlevel, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve 6.1×/7.5× execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics.

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Section: Discussionmentioning

confidence: 99%

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Tang

Giacomin

Micheli

et al. 2019

IEEE Trans. VLSI Syst.

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“…In this paper, we consider a commercial CMOS 40nm technology, whose nominal working voltage is VDD = 0.9V . We use the Stanford RRAM model [14], which physically models an ideal memory, with the following parameters: RLRS = 2k⌦, RHRS = 27M ⌦, Iset = 500µA, Vset = Vreset = 1.2V , which are sufficient to guarantee that the RRAM-based circuits are as power efficient as SRAM-based circuits [5]. In high fan-in and low fan-out condition, where the delay is dominated by the multiplexing structure, RRAM-based multiplexer can achieve 67% reduction in delay, thanks to its smaller capacitances.…”

Section: Introductionmentioning

confidence: 99%

Optimization opportunities in RRAM-based FPGA architectures

Tang

Micheli

Gaillardon

2017

2017 IEEE 8th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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Abstract-Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures typically avoiding the use of large multiplexers. Resistive Random Access Memory (RRAM)-based multiplexers, built with one-level structure, have a unique advantage over SRAM-based multiplexers: their ideal delay is independent from the input size. This property allows RRAM-based FPGA architectures to use larger multiplexers than their SRAM-based counterparts, without generating any delay overhead. In this paper, by carefully considering the properties of RRAM multiplexers, we assess that current state-ofart architectural parameters for SRAM-based FPGAs cannot preserve optimality in the context of RRAM-based FPGAs. As a result, we propose that in RRAM-based FPGAs, (a) the routing tracks should be interconnected to Look-Up Table (LUT) inputs via a one-level crossbar, instead of through Connection Blocks and local routing; (b) the Switch Blocks should employ larger multiplexers; (c) length-2 wires should be used instead of length-4 wires. When operated in nominal voltage, the proposed RRAM-based FPGA architecture reduces area by 26%, delay by 39% and channel width by 13%, as compared to a SRAM-based FPGA with a classical architecture. When operated in the near-Vt regime, the proposed RRAM-based FPGA architecture improves Area-Delay Product by 42% and Power-Delay Product by 5⇥ as compared to a classical SRAM-based FPGA at nominal voltage.

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