A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Gaillardon, Pierre-Emmanuel; Tang, Xianglu; Sandrini, Jury; Thammasack, Maxime; Omam, Somayyeh Rahimian; Sacchetto, Davide; Leblebici, Yusuf; Micheli, Giovanni De

doi:10.7873/date.2015.1112

Cited by 11 publications

(2 citation statements)

References 13 publications

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“…The LUT consists of a tree-like multiplexer and an array of SRAM cells. Figure 2 shows the basic structure of the LUT and SRAM cell in an FPGA [23,24]. When the designer programs the SRAM-based FPGA, SRAM cells store the configuration data of the logic function and routing data of the connections between CLBs.…”

Section: Sram-based Field-programmable Gate Array (Fpga)mentioning

confidence: 99%

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Yang,

Tanavardi Nasab,

Thapliyal

2024

Electronics

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Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T.

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Section: Sram-based Field-programmable Gate Array (Fpga)mentioning

confidence: 99%

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Yang,

Tanavardi Nasab,

Thapliyal

2024

Electronics

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“…So far, various metal oxides using different materials with the resistive switching characteristics between two high and low resistance values are fabricated that are called Resistive Random Access Memory (RRAMs) [1]. RRAMs are of high interest due to their promising applications in non-volatile memory design [2], [3], digital and analog programmable systems [4], [5], [6], and neuromorphing computing [7]. In 1971, Chua [8] derived equations describing a forth passive circuit element from symmetry which he called memristor, short for memory resistor.…”

Section: Introductionmentioning

confidence: 99%

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

Shirinzadeh

Soeken

Gaillardon

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed MajorityInverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMPbased realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing-particularly in MAJ-based realizations-and the use of techniques proposed for optimization.

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Shirinzadeh¹,

Drechsler²

2019

In-Memory Computing

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A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

Cited by 11 publications

References 13 publications

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

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