Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

Abstract

Abstract-Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed MajorityInverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMPbased realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing-particularly in MAJ-based realizations-and the use of techniques proposed for optimization.

Endurance management for resistive Logic-In-Memory computing architectures

“…both area and latency when using MajorityInverter Graphs (MIG, [18]) [19]. Regarding write endurance, RM 3 has more flexibility in comparison with IMP by sharing the writes between three operands instead of one.…”

“…In general MIGs can be efficiently exploited for logicin-memory computing due to benefiting from the resistive majority property enabled by RM 3 [19], [21].…”

“…An extended inverter propagation axiom from right to left denoted by Ω.I R→L(1−3) was proposed in [19] to control the extra costs caused by complemented edges. Ω.I R→L(1−3) includes the three transformations (1) xȳz = xyz , (2) xȳz = xyz , and (3) xȳz = xyz .…”

An MIG-based compiler for programmable logic-in-memory architectures

“…Logic circuits using the resistive switching proposed so far are mostly based on logic implementation that imposes long sequences of operations. Very recently a majority oriented logic has been proposed for synthesis of RRAM-based logic circuits that shows much lower latency and area overhead compared to the sequential implication based approach [13]. In [7], a computer architecture using only RRAMs called Programmable Logic-in-Memory (PLiM) was proposed.…”

“…An optimization algorithm based on MIG rewriting [1,13] that optimizes the MIG w.r.t. the expected number of instructions and required RRAMs in the translated PLiM program.…”