An MIG-based compiler for programmable logic-in-memory architectures

Abstract

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on resistive memory arrays. Our approach uses Majority-Inverter Graphs (MIGs) to manage the computational operations. In order to obtain a performance and resource efficient program, we employ optimization techniques both to the underlying MIG as well as to the compilation procedure itself. In addition, our proposed approach optimizes the program with respect to memory endurance constraints which is of particular importance for in-memory computing architectures.

Endurance management for resistive Logic-In-Memory computing architectures

“…In general MIGs can be efficiently exploited for logicin-memory computing due to benefiting from the resistive majority property enabled by RM 3 [19], [21].…”

“…To execute a Boolean function, PLiM translates its MIG representation to a set of RM 3 instructions. Implementing logic operations within memory cells requires to control the distribution of signals and the scheduling of operations considering latency, area, and management [11], [21].…”

“…3) PLiM Compiler: An MIG-based compiler for PLiM was proposed in [21], which aims at optimizing the resulting programs w.r.t. the number of instructions and RRAM devices.…”

“…Algorithm 1 shows the MIG rewriting proposed for PLiM compiler [21]. A cycle of the algorithm starts with conventional MIG rewriting for node minimization proposed in [18], [20] (steps 2-4) and terminates with the extension of inverter propagation axioms (steps 5-6) to tackle the issue of complemented edges.…”

“…A cycle of the algorithm starts with conventional MIG rewriting for node minimization proposed in [18], [20] (steps 2-4) and terminates with the extension of inverter propagation axioms (steps 5-6) to tackle the issue of complemented edges. A compilation approach including two parts of node selection and translation was also proposed in [21] to reduce the number of RRAM devices for PLiM implementations. The node selection aims at finding an order for computing nodes of a given MIG which results in a smaller number of RRAMs, while the node translation chooses the operands of RM 3 to compute a node with the minimum number of instructions and RRAMs.…”