Energy-efficient and reference-free monotonic capacitor switching scheme with fewest switches for SAR ADC

Abstract

A novel switching scheme for low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive approximation register (SAR) analogue to-digital converters (ADCs) is presented which requires only 2 references, V REF and ground. With the monotonic capacitor switching procedure and C-2C dummy capacitor, the proposed switching scheme achieves 90.61% less switching energy, 74.7% less area and 41.18% less number of switches compared to conventional architecture, which results in an energy-efficient and switch-fewest switching scheme. Behavioral simulation results prove the effectiveness of the proposed switching scheme.

Energy-efficient, area-efficient, high-accuracy and low-complexity switching scheme for SAR ADC

“…In the proposed switching scheme, only the least significant bit (LSB) is depended on the accuracy of V cm , and moreover, only two reference voltages are used for each capacitor. Furthermore, the common-mode voltage of the proposed switching scheme shifts by V ref =4 which is the same as that of VMS [10], and less than those of the switching schemes [6,7,8,9,11]. …”

“…Among the building blocks in a SAR ADC, a capacitive DAC always consumes a significant part of the total power consumption [3,4,5]. Recently, several energy-efficient techniques have been developed to improve the power efficiency of DAC capacitor arrays [6,7,8,9,10,11]. Compared to conventional technique [12], Split Capacitor [6], Set-and-down [7], Wang [8], Tri-level [9], VMS [10], Hybrid [11] reduce the switching energy by 37.48%, 81.26%, 90.61%, 96.89%, 97.66% and 98.83%, respectively.…”

“…Recently, several energy-efficient techniques have been developed to improve the power efficiency of DAC capacitor arrays [6,7,8,9,10,11]. Compared to conventional technique [12], Split Capacitor [6], Set-and-down [7], Wang [8], Tri-level [9], VMS [10], Hybrid [11] reduce the switching energy by 37.48%, 81.26%, 90.61%, 96.89%, 97.66% and 98.83%, respectively. Tri-level [9], VMS [10] and Hybrid [11] are great energy efficient with switching energy reduced by more than 95%.…”

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

“…Among the building blocks in a SAR ADC, a capacitive DAC always consumes a significant part of the total power consumption. Several switching schemes [1][2][3][4] have been proposed to improve the power efficiency of capacitive DAC. In this paper, a more energy-efficient and area-efficient switching scheme is proposed and implemented in a 180 nm CMOS technology.…”

Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics

“…In these applications, the successiveapproximation-register (SAR) ADCs, especially charge scaling SAR ADCs, are prevalent options for low-power A/D conversion. Recently, many publications are about the research on reducing the switching power of the D/A network in SAR ADC [1][2][3][4][5][6][7][8]. In [1], energy saving is achieved by splitting the most-significant bit (MSB) into several binary scaled capacitors.…”