Ending Piracy of Integrated Circuits

Roy, Jarrod A.; Koushanfar, Farinaz; Markov, Igor L.

doi:10.1109/mc.2010.284

Cited by 305 publications

(180 citation statements)

References 6 publications

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“…We expect this trend to further intensify for the complex and diverse 3D integration landscape, thereby increasing the risk exposure for 3D chips. To address and manage this challenge of verification and other security-centric challenges, the notions of "secure by design" and "design-for-trust" have been promoted for some years now for "regular" 2D chips [116], [117], [118], [119], [123], [124], [125], [126], [127], [128]. Similar studies are recently focusing on 3D chips as well [129], [130], [131], [132], [133], [134], [135], [136], [137], [138].…”

Section: Towards Trustworthy 3d Integrationmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Towards Trustworthy 3d Integrationmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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“…In [19][20][21], the authors presented a technique to insert XOR/XNOR gates randomly into an original circuit to conceal its functionality. Upon inserting the valid key, the end-user can get the correct output.…”

Section: Prior Workmentioning

confidence: 99%

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Alasad

Yuan

2017

Electronics

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Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique.

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“…sated by error correction). State-of-the-art hardware metering approaches [16] combine unclonable identifiers with locking/unlocking functionality: the circuit is nonfunctional upon fabrication and must receive a unique unlocking sequence in order to start working. This sequence is calculated by the designer from the unclonable identifier data provided by the manufacturer, but cannot be calculated by the manufacturer alone.…”

Section: Counterfeiting and Hardware Meteringmentioning

confidence: 99%

“…The unlocking circuitry present in every circuit incorporates the designer's public key, and the circuit becomes functional only if the unlocking sequence has been created based on the designer's private key. Practical protocols are more complex in order to eliminate several further vulnerabilities [16].…”

Section: Counterfeiting and Hardware Meteringmentioning

confidence: 99%

Hardware security and test: Friends or enemies?

Polian

2014

It - Information Technology

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Abstract:Hardware security is a relatively new scientific discipline which focuses on adversarial threats to hardware components of complex systems and infrastructures, including manipulation, unauthorized access to confidential data, and intellectual property theft. State-of-the-art test methods can contribute to detection and elimination of security threats but also may introduce new vulnerabilities. This article will explain this dichotomy and outline current research challenges.

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Ending Piracy of Integrated Circuits

Cited by 305 publications

References 6 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

E2LEMI:Energy-Efficient Logic Encryption Using Multiplexer Insertion

Hardware security and test: Friends or enemies?

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