Encountering gate oxide breakdown with shadow transistors to increase reliability

Cornelius, Claas; Sill, Frank; Sämrow, Hagen; Salzmann, Jakob; Timmermann, Dirk; Silva, Diógenes da

doi:10.1145/1404371.1404407

Cited by 4 publications

(3 citation statements)

References 21 publications

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“…Further investigations concentrate on the application of more complex failure models and on algorithms to selectively implement redundancy. Such algorithms promise to adaptively trade area and delay penalties with improvements of the MTTF [20].…”

Section: Resultsmentioning

confidence: 99%

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Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits

Cornelius¹,

Torres²,

Timmermann³

2011

Journal of Low Power Electronics

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CMOS is furthermore the most widespread technology for digital designs as no feasible alternative is in sight to date and in the near future. The fundamental causes for this supremacy so far are the capability for miniaturization as well as the reliability and robustness of CMOS. Against the background of nanotechnology though, reliability concerns are arising with an alarming pace. The consequence is an increasing demand for approaches to improve both yield and lifetime reliability of today's complex integrated systems. Hence, a common solution is the redundant implementation of components. However, redundancy contradicts those other efforts in order to cope with power dissipation. Thus, the essential contribution of this work is an approach that increases the lifetime reliability of integrated circuits while delay and power penalties are kept to a minimum. Accordingly, "Sleep Transistors" (as a common technique to reduce standby leakage) are combined with the idea of modular redundancy. Furthermore, we propose an extended flow for the quantification of reliability on transistor level. Finally, the presented simulation results evidence that the suggested approach increases the lifetime reliability by more than a factor of two compared to initial designs.

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Section: Resultsmentioning

confidence: 99%

“…Thus, the impact of failure mechanisms (like electromigration, TDDB and NTBI) are also correspondingly smaller. Nevertheless, it is reasonable to apply special design strategies for the multiplexers as well, like transistors with thicker gate oxide [20] and wider wires.…”

Section: Additional Logicmentioning

confidence: 99%

Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits

Cornelius¹,

Torres²,

Timmermann³

2011

Journal of Low Power Electronics

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“…Therefore, redundant transistors are inserted randomly into the design to increase yield as regards stuck-open transistors. This idea was extended in [10] where the redundant Shadow Transistors were inserted only at those instances that are most vulnerable to TDDB which increases not just the yield but also lifetime reliability. By inserting transistors with higher gate oxide thickness than the original ones, reliability could be increased even more.…”

Section: Motivationmentioning

confidence: 99%

Twin logic gates

Saemrow

Cornelius

Sill

et al. 2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and yield concerns. So far, only very little research efforts have been put into lowlevel approaches for lifetime reliability, whereas lots of efforts have focused on soft-errors and system-level solutions. In this paper, we introduce and compare three diverse design approaches which apply redundancy on different abstraction levels to enhance the reliability of a Wallace multiplier as regards gate oxide breakdown. The results of the test design were further improved by adding transistors and gates with different gate oxide thicknesses. The achieved results show that lifetime reliability increases up to 200 % at constant delay by adding redundant gates, subsequently called Twin Logic Gates. However, this comes at the price of overhead for area as well as power consumption. Furthermore, it needs to be noted that the presented strategies can additionally improve defect yield.

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