Gate oxide tunneling current I gate and sub-threshold current I sub dominate the leakage of designs. The latter depends on threshold voltage V th while I gate vary with the thickness of gate oxide layer T ox . In this paper, we propose a new method that combines approaches of Dual Threshold CMOS (DTCMOS), mixed-T ox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant.
The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V th (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V th (DVT) gate-level techniques.
Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Traditionally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards operational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does improve system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an algorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transistors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark circuits and prove the combined approach successful. The enhanced designs were on average 41.8 % more reliable compared to the initial designs in respect of TDDB at the price of moderately increased power consumption and delay.
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