Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory

Luo, Yi; Ghose, Saugata; Cai, Yu; Haratsch, Erich F.; Mutlu, Onur

doi:10.1109/jsac.2016.2603608

Cited by 74 publications

(131 citation statements)

References 31 publications

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“…• P/E cycling error in 3D NAND flash memory follows a linear trend, which is similar to that in planar NAND flash memory using an older manufacturing process technology node (e.g., 20-24 nm) [14]. However, in sub-20 nm planar NAND flash memory, P/E cycling error exhibits a power law trend [64,81] (Appendix A.1.2). • 3D NAND flash memory experiences 40% less program interference than 20-24 nm planar NAND flash memory (Appendix A.1.3).…”

Section: Other Error Characteristicsmentioning

confidence: 65%

“…Figure 1a shows the four possible states (i.e., ER, P1, P2, P3) in MLC NAND flash memory, along with their corresponding bit values. As a result of manufacturing process variation, the threshold voltage of cells programmed to the same state follow a Gaussian-like distribution across the voltage window of the state [9,14,64,81], depicted as a probability density curve in Figure 1a. A NAND flash memory chip contains thousands of flash blocks, which are two-dimensional arrays of flash cells.…”

Section: Nand Flash Memory Basicsmentioning

confidence: 99%

“…Write-induced errors occur during program or erase operations. P/E cycling errors (or program/erase variation errors) [14,64,81] are errors that occur immediately after erasing and programming a flash page. These errors occur because of the inaccuracy of each program and erase operation.…”

Section: Errors In Nand Flash Memorymentioning

confidence: 99%

“…First, we perform a detailed characterization and analysis of three error characteristics that are drastically different in 3D NAND flash memory than in planar NAND flash memory: layer-to-layer process variation (Section 4.2), early retention loss (Section 4.3), and retention interference (Section 4.4). In addition to identifying new error sources in 3D NAND flash memory, we use our methodology to corroborate and quantify 3D NAND error characteristics that are a result of error sources that were previously identified in planar NAND flash memory, including retention loss [6-9, 11, 23, 80], P/E cycling [9,11,14,64,80,81], program interference [4,9,11,15,16,80], read disturb [5,9,11,81], and process variation [13,84]. We summarize our findings for these error types in Section 4.5, and provide detailed results on our characterization of these previously-identified error sources in Appendix A.…”

Section: Characterization Of 3d Nand Flash Memory Errorsmentioning

confidence: 99%

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Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

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Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory.In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell.Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

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Section: Other Error Characteristicsmentioning

confidence: 65%

Section: Nand Flash Memory Basicsmentioning

confidence: 99%

Section: Errors In Nand Flash Memorymentioning

confidence: 99%

Section: Characterization Of 3d Nand Flash Memory Errorsmentioning

confidence: 99%

See 2 more Smart Citations

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

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“…There have been recent large-scale field studies a well as small-scale controlled studies of real memory errors on real devices and systems, showing that both DRAM and NAND flash memory technologies are becoming less reliable [82, 78, 98-100, 77, 93, 28, 27, 74, 73, 17, 25, 79, 84, 80]. As detailed experimental analyses of real DRAM and NAND flash chips show, both technologies are becoming much more vulnerable to cell-to-cell interference effects [82,55,26,22,20,17,21,81,72,23,28,27,79,80], data retention is becoming significantly more difficult in both technologies [69,47,70,49,89,31,46,75,25,18,71,17,21,19,81,48,28,27,74,73,82,79], and error variation within and across chips is increasingly prominent [70,63,30,29,17,21,64,[51]…”

Section: Other Potential Vulnerabilitiesmentioning

confidence: 99%

RowHammer and Beyond

Mutlu

2019

Constructive Side-Channel Analysis and Secure Design

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We will discuss the RowHammer problem in DRAM, which is a prime (and likely the first) example of how a circuit-level failure mechanism in Dynamic Random Access Memory (DRAM) can cause a practical and widespread system security vulnerability. RowHammer is the phenomenon that repeatedly accessing a row in a modern DRAM chip predictably causes errors in physically-adjacent rows. It is caused by a hardware failure mechanism called read disturb errors. Building on our initial fundamental work that appeared at ISCA 2014, Google Project Zero demonstrated that this hardware phenomenon can be exploited by user-level programs to gain kernel privileges. Many other recent works demonstrated other attacks exploiting RowHammer, including remote takeover of a server vulnerable to RowHammer. We will analyze the root causes of the problem and examine solution directions. We will also discuss what other problems may be lurking in DRAM and other types of memories, e.g., NAND flash and Phase Change Memory, which can potentially threaten the foundations of reliable and secure systems, as the memory technologies scale to higher densities.

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