A Modern Primer on Processing in Memory

Mutlu, Onur; Ghose, Saugata; Gómez-Luna, Juan; Ausavarungnirun, Rachata

doi:10.1007/978-981-16-7487-7_7

Cited by 47 publications

(25 citation statements)

References 300 publications

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“…Modern 3D-stacked memories [221][222][223] such as High Bandwidth Memory [221] and the Hybrid Memory Cube [222] include logic layers that have access to the high memory bandwidth available within a 3D-stacked memory chip [75]. We evaluate the opportunities a 3D-stack-based PNM architecture provides for NN inference.…”

Section: Nn Inference On Specialized 3d-based Processing-near-memorymentioning

confidence: 99%

“…Similarly, various approaches to improve the performance of memory-bound NNs have been proposed [45,[63][64][65][66][67][68][69][70][71][72][73]. One such approach is processing-in-memory (PIM) [74][75][76][77][78][79][80][81][82][83][84][85], where computation is (1) placed near 2D [69, or 3D [45,63,64,67, memory arrays (processing-nearmemory, PNM) or (2) performed using the memory arrays themselves (processingusing-memory, PUM) [65, 70-72, 135, 167-203]. 1 PNM and PUM can be implemented using different memory technologies [75], including SRAM [71,99,107,110,177,178], DRAM [45, 64, 87, 100, 111, 123, 125, 128, 131-135, 142, 143, 146, 152, 157, 193, 195, 196], and resistive RAM (ReRAM) [65,70,121,174,175,183,188,…”

Section: Introductionmentioning

confidence: 99%

“…One such approach is processing-in-memory (PIM) [74][75][76][77][78][79][80][81][82][83][84][85], where computation is (1) placed near 2D [69, or 3D [45,63,64,67, memory arrays (processing-nearmemory, PNM) or (2) performed using the memory arrays themselves (processingusing-memory, PUM) [65, 70-72, 135, 167-203]. 1 PNM and PUM can be implemented using different memory technologies [75], including SRAM [71,99,107,110,177,178], DRAM [45, 64, 87, 100, 111, 123, 125, 128, 131-135, 142, 143, 146, 152, 157, 193, 195, 196], and resistive RAM (ReRAM) [65,70,121,174,175,183,188,189,199,200,202]. Independent of the memory technology, PIM allows NNs to enjoy higher memory bandwidth, shorter memory access latency, and lower energy per bit [75].…”

Section: Introductionmentioning

confidence: 99%

“…1 PNM and PUM can be implemented using different memory technologies [75], including SRAM [71,99,107,110,177,178], DRAM [45, 64, 87, 100, 111, 123, 125, 128, 131-135, 142, 143, 146, 152, 157, 193, 195, 196], and resistive RAM (ReRAM) [65,70,121,174,175,183,188,189,199,200,202]. Independent of the memory technology, PIM allows NNs to enjoy higher memory bandwidth, shorter memory access latency, and lower energy per bit [75].…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we focus on DRAM-based PIM, and NN inference in three different DRAM-based PIM architectures: (1) UPMEM [88, 90-92, 204, 205], a large-scale 2D-based PNM architecture, which integrates several simple general-purpose processing cores near DRAM arrays (inside a DRAM chip); (2) Mensa [45], a heterogeneous edge NN inference accelerator, which uses 3D-stack-based PNM to speed up memory-bound NN models; and (3) SIMDRAM [206], a PUM architecture, 1 There is no consensus on the terminology related to processing-in-memory in the current literature. However, we borrow the terms "processing-near-memory" (PNM) and "processing-using-memory" (PUM) from [75], which clearly defines these two terms and demonstrates that existing PIM techniques fall into one of these two categories.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud

F.¹,

Gómez-Luna²,

Ghose³

et al. 2022

Preprint

Self Cite

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Neural networks (NNs) are growing in importance and complexity. A neural network's performance (and energy efficiency) can be bound either by computation or memory resources. The processing-in-memory (PIM) paradigm, where computation is placed near or within memory arrays, is a viable solution to accelerate memory-bound NNs. However, PIM architectures vary in form, where different PIM approaches lead to different trade-offs. Our goal is to analyze, discuss, and contrast DRAM-based PIM architectures for NN performance and energy efficiency. To do so, we analyze three state-of-the-art PIM architectures: (1) UPMEM, which integrates processors and DRAM arrays into a single 2D chip; (2) Mensa, a 3D-stack-based PIM architecture tailored for edge devices; and (3) SIMDRAM, which uses the analog principles of DRAM to execute bit-serial operations. Our analysis reveals that PIM greatly benefits memory-bound NNs: (1) UPMEM provides 23× the performance of a high-end GPU when the GPU requires memory oversubscription for a general matrix-vector multiplication kernel; (2) Mensa improves energy efficiency and throughput by 3.0× and 3.1× over the Google Edge TPU for 24 Google edge NN models; and (3) SIMDRAM outperforms a CPU/GPU by 16.7×/1.4× for three binary NNs. We conclude that the ideal PIM architecture for NN models depends on a model's distinct attributes, due to the inherent architectural design choices.

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Section: Nn Inference On Specialized 3d-based Processing-near-memorymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud

F.¹,

Gómez-Luna²,

Ghose³

et al. 2022

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

Processing‐in‐memory based multilateration localization in wireless sensor networks using memristor crossbar arrays

Mohammed Siyad,

Mohan

2024

Concurrency and Computation

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SummaryMost of the multilateration algorithms for object localization rely heavily on matrix multiplication for calculating the precise location of the target from all the reference points in a 3D domain. A significant disadvantage is that performing matrix multiplication can be computationally expensive, particularly for larger matrices, leading to slower performance and longer processing times. In this article, we propose a Processing‐in‐Memory (PIM) based localization approach for multilateration using a memristor crossbar array for performing faster matrix multiplication. The experiments were conducted on real‐time data collected through ultra‐wideband (UWB) chip. The simulation results demonstrate that the proposed model is around 50% faster than the fastest known localization algorithm considered for evaluation and exhibits an average of 55% improvement in localization accuracy.

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Memristor-Based In-Memory Computing Architecture for Scientific Computing

Li²,

Ling³

et al. 2022

Memristor Computing Systems

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The advancement in the field of machine learning is inextricably linked with the concurrent progress in domain-specific hardware accelerators such as GPUs and TPUs. However, the rapidly growing computational demands necessitated by larger models and increased data have become a primary bottleneck in further advancing machine learning, especially in mobile and edge devices. Currently, the neuromorphic computing paradigm based on memristors presents a promising solution. In this study, we introduce a memristorbased MobileNetV3 neural network computing paradigm and provide an end-to-end framework for validation. The results demonstrate that this computing paradigm achieves over 90% accuracy on the CIFAR-10 dataset while saving inference time and reducing energy consumption. With the successful development and verification of MobileNetV3, the potential for realizing more memristor-based neural networks using this computing paradigm and open-source framework has significantly increased. This progress sets a groundbreaking pathway for future deployment initiatives.

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A Modern Primer on Processing in Memory

Cited by 47 publications

References 300 publications

Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud

Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud

Processing‐in‐memory based multilateration localization in wireless sensor networks using memristor crossbar arrays

Memristor-Based In-Memory Computing Architecture for Scientific Computing

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