Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Abstract

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory.In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell.Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

RowHammer: A Retrospective

“…As such, it is critical to understand the issues with data retention in flash memory. Our recent work provides detailed experimental analysis of data retention behavior of planar and 3D MLC NAND flash memory [50,52,53,167,168]. We show, among other things, that there is a wide variation in the leakiness of different flash cells: some cells leak very fast, some cells leak very slowly.…”

“…We believe that, as memory technologies scale to higher densities, other problems may start appearing (or may already be going unnoticed) that can potentially threaten the foundations of secure systems. There have been recent largescale field studies of memory errors showing that both DRAM and NAND flash memory technologies are becoming less reliable [42,50,52,53,167,168,171,172,175,176,183,196,214,[227][228][229]. As detailed experimental analyses of real DRAM and NAND flash chips show, both technologies are becoming much more vulnerable to cell-to-cell interference effects [42, 45-48, 51-53, 133, 166, 175, 176, 178, 183], data retention is becoming significantly more difficult in both technologies [42-44, 46, 50, 52, 53, 59, 113, 115-117, 160, 161, 164, 167-169, 175, 178, 183, 203], and error variation within and across chip, and across operating conditions, is increasingly prominent [42, 46, 55, 57, 125-127, 147, 151, 161].…”

“…NAND Flash Data Retention Issues Experimental analysis of modern flash memory devices show that the dominant source of errors in flash memory are data retention errors [42,52]. As a flash cell wears out, its charge retention capability degrades [42,50,52,53,167,168,171,214] and the cell becomes leakier. As a result, to maintain the original data stored in the cell, the cell needs to be refreshed [43,44].…”

Error source and latency-aware read performance optimization scheme for aged SSDs

“…Wu et al measured the RBER variation before and after performing these four operations, and they also found that the P/E cycles and retention time are the main error source for 3D NAND flash [8]. The same result can be found in [26,27,29,30]. According to the research work [32,33], we plots the RBER induced by different error sources as shown in 1.…”

RowHammer and Beyond

“…There have been recent large-scale field studies a well as small-scale controlled studies of real memory errors on real devices and systems, showing that both DRAM and NAND flash memory technologies are becoming less reliable [82, 78, 98-100, 77, 93, 28, 27, 74, 73, 17, 25, 79, 84, 80]. As detailed experimental analyses of real DRAM and NAND flash chips show, both technologies are becoming much more vulnerable to cell-to-cell interference effects [82,55,26,22,20,17,21,81,72,23,28,27,79,80], data retention is becoming significantly more difficult in both technologies [69,47,70,49,89,31,46,75,25,18,71,17,21,19,81,48,28,27,74,73,82,79], and error variation within and across chips is increasingly prominent [70,63,30,29,17,21,64,[51]…”