Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates

Lau, John H.; Zhang, M. S.; Lee, S. W. Ricky

doi:10.1115/imece2010-40974

Cited by 13 publications

(3 citation statements)

References 5 publications

(10 reference statements)

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“…To extend the application of the presented approach for the high-power LED chip, the heat dissipation is a critical issue. In this regard, the bottom side of the LED chip should directly connect to thermal dissipation pad [14]. Note the reliability tests, such as the environment aging test and robust test in structure, are not available in this study.…”

Section: Discussionmentioning

confidence: 99%

‘Flip glass substrate’ package technology for LED yield and performance enhancement

Chang-Chien

Huang

Yip

et al. 2012

J. Micromech. Microeng.

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This study presents the 'flip glass substrate' approach for the package of an LED chip. The transparent glass substrate covered with phosphor is employed as the carrier. This LED package scheme and its related processes have three merits: (1) light is allowed to emit in all directions for the LED packaged in a flipped glass substrate, and thus the view angle is increased, (2) the chromaticity coordinate distribution of the glass substrate coated with phosphor could be evaluated before LED chip is packaged. Thus glass substrate with wrong chromaticity coordinates could be reworked in early stage, and the color bin yield is enhanced and (3) the uniformity of angular CCT (correlated color temperature) for the LED packaged in the flip glass coated with phosphor is much better than the commercial LED packaged with random distributed phosphor. In application, the glass substrate for packaging is implemented and tested. Measurements show that the packaging technology provides a wide and symmetry view angle (140 • ± 1.5 • ) for the LED chip. In comparison, 95% of the existing commercial single-chip LED packages have a view angle of less than 125 • . The maximum deviation in angular CCT is 1300 K, whereas the CCT is 2500 K for random-distributed phosphor type LED.

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Section: Discussionmentioning

confidence: 99%

‘Flip glass substrate’ package technology for LED yield and performance enhancement

Chang-Chien

Huang

Yip

et al. 2012

J. Micromech. Microeng.

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“…This novel structural offers low-profile optoelectronic packaging for chipto-chip optical interconnects. Optical, thermal management and mechanical performances have been demonstrated [48] by simulations based on optic theory, heat-transfer theory, and continuum mechanics.…”

Section: (66) Interposer Used As Thermal Management Tools For 3d Ic I...mentioning

confidence: 99%

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

Lau

2012

ECS Trans.

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"There's Plenty of Room at the Bottom" is the title of Richard Feynman's lecture on December 29th, 1959 to the American Physical Society at California Institute of Technology (Caltech) and is generally considered to be the very first speech about nanotechnology. Some important milestones of nanotechnology will be briefly mentioned and the emphasis is placed on the applications and outlooks of nanotechnology in electronics. "Computing Machines in the Future" is the title of the Nishina Memorial Lecture at Gakushuin University in Tokyo given by the 1965 Nobel Physics Laureate, Richard Feynman on August 9th, 1985. During the lecture, Feynman not only told us to go for 3D integration, but also taught us how to do it! In this study, 3D integration will be the focus and the emphasis is placed on 3D IC integration and their recent advances and new trends. 3D Si integration will be briefly discussed

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“…Comparing to other interconnection technologies such as the wire bonding, the advantages of TSV are [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]:…”

Section: Introductionmentioning

confidence: 99%

Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

Hung

Lau

Chen

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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In this study, a method to test blind TSVs in 3D IC integration for their electrical performance is investigated. Emphasis is placed on the development of a novel blind-TSV method by electrical testing on the top side of the TSV-wafer before backgrinding. Through leakage current testing, it is possible to determine whether there is short circuit between blind TSVs. Most conventional measurement methods can only be performed after wafer thinning to reveal the TSVs Cu and/or backside processing, which could lead to a higher manufacturing cost of 3D IC integration products if the electrical performances of the manufactured TSV don't meet the specification.Also, by providing analysis flow of high frequency simulation and measurement, we can define the thickness of the isolation layer (Silicon dioxide, SiO 2 ) of blind TSV into specification. Furthermore, the analysis flow can obtain the important high-frequency parameter of silicon material such as silicon conductivity. Finally, the SEM images of cross sections verify the current findings.

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Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates

Cited by 13 publications

References 5 publications

‘Flip glass substrate’ package technology for LED yield and performance enhancement

‘Flip glass substrate’ package technology for LED yield and performance enhancement

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

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