EMAXVR: A programmable accelerator employing near ALU utilization to DSA

Ichikura, Takahiro; Yamano, Ryusuke; Kikutani, Yuma; Zhang, Renyuan; Nakashima, Yasuhiko

doi:10.1109/coolchips.2018.8373078

Cited by 4 publications

(5 citation statements)

References 5 publications

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“…In the hash update step, the final 256-bit hash value, which is divided into 8 chunks of 32-bit data HO 0 , HO 1 ,...,HO 7 , is computed by adding the initial hashes H 0 , H 1 ,...,H 7 to the loop hashes a, b, c, d, e, f, g, h, as illustrated in eq. (13). Third, data dependence among the loops is present.…”

Section: Background a Sha-256 Algorithmmentioning

confidence: 99%

“…Despite these disadvantages, multicore CPUs and GPUs are currently considered to be the most applicable hardware platforms for calculating SHA-256 in Bitcoin mining and other blockchain networks. In another approach, the systolic array-based accelerator named EMAXVR in [13] and its improved version in [14] were applied to reduce the data access time by implementing local memory near the ALU. Although this platform achieves high performance on image processing and AI learning [13], [14], its performance for computing SHA-256 is very poor [15].…”

Section: Background a Sha-256 Algorithmmentioning

confidence: 99%

“…In another approach, the systolic array-based accelerator named EMAXVR in [13] and its improved version in [14] were applied to reduce the data access time by implementing local memory near the ALU. Although this platform achieves high performance on image processing and AI learning [13], [14], its performance for computing SHA-256 is very poor [15]. The key reason for the low processing rate is the data-dependent characteristic of the SHA-256 algorithm, as mentioned above.…”

Section: Background a Sha-256 Algorithmmentioning

confidence: 99%

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A High-Performance Multimem SHA-256 Accelerator for Society 5.0

2021

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The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an applicationspecific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized 8.5mm × 8.5mm, consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

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Section: Background a Sha-256 Algorithmmentioning

confidence: 99%

Section: Background a Sha-256 Algorithmmentioning

confidence: 99%

Section: Background a Sha-256 Algorithmmentioning

confidence: 99%

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A High-Performance Multimem SHA-256 Accelerator for Society 5.0

2021

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“…Although systolic arrays are less programmable than von Neumann computing platforms, the configurability is promising for arranging many data streams among ALUs, LMMs, and external memory in parallel. The utilization ratio of the ALUs and the traffic between external memory and LMM are comparable with state-of-the-art DSAs [21]. However, the first problem is unavoidable: wide memory bandwidth.…”

Section: Problems With Conventional and Modern Systolic Arraysmentioning

confidence: 83%

Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth

Iwamoto

Kikutani

Zhang

et al. 2020

IEICE Trans. Inf. & Syst.

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Jun IWAMOTO †a) , Yuma KIKUTANI †b) , Renyuan ZHANG †c) , Members, and Yasuhiko NAKASHIMA †d) , Fellow SUMMARY A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. In this paper, we propose the following to improve the footprint and the scalability of systolic arrays: (1) column multithreading for reducing the number of physical units and maintaining the performance even for back-to-back floating-point accumulations; (2) a cascaded peer-to-peer AXI bus for a scalable multichip structure and an intra-chip parallel local memory bus for low latency; (3) multilevel loop control in any unit for reducing the startup overhead and adaptive operation shifting for efficient reuse of local memories. We designed a systolic array with a single column × 64 row configuration with Verilog HDL, evaluated the frequency and the performance on an FPGA attached to a ZYNQ system as an AXI slave device, and evaluated the area with a TSMC 28nm library and memory generator and identified the following: (1) the execution speed of a matrix multiplication/a convolution operation/a light-field depth extraction, whose size larger than the capacity of the local memory, is 6.3× / 9.2× / 6.6× compared with a similar systolic array (EMAX); (2) the estimated speed with a 4-chip configuration is 19.6× / 16.0× / 8.5×; (3) the size of a single-chip is 8.4 mm 2 (0.31× of EMAX) and the basic performance per area is 2.4×.

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“…We believe that with their high computational and memory resources, reprogrammable hardware design, low power consumption, and high optimization for parallel pipeline processes, FPGAs are well suited for Scrypt implementation. There are several high-performance architectures that can be applied on FPGAs to reduce the memory access time, such as the systolic-array-based accelerator called EMAXVR [41], [42] used in near-memory computing. However, despite exhibiting high performance in machine learning and image processing applications, they can achieve only poor performance when performing low-cost operator hash functions [43].…”

Section: Preliminary Idea and Motivation For The High-performance Multi Romix Scrypt Acceleratormentioning

confidence: 99%

MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security

Tran²,

Pham

et al. 2021

IEEE Access

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The development of low-energy, high-performance hardware for cryptocurrency mining is gaining widespread attention. The mining process for proof-of-work (PoW) in conventional cryptocurrencies' blockchains is increasingly being replaced by application-specific integrated circuits (ASICs). This leads to many security threats for the blockchain network because it decreases security and increases power consumption for mining. Therefore, Scrypt, the most representative ASIC-resistant algorithm, was developed to solve this problem. However, there are still some problems and challenges with the current Scrypt hardware. This article presents a new hardware architecture for the Scrypt algorithm intended for a PoW-based cryptocurrency mining system. The proposed Multi ROMix Scrypt Accelerator (MRSA) hardware architecture applies several optimization techniques: configuration, local-memory computing with high-performance pipelined Multi ROMix and rescheduling resources to significantly increase processing speed, flexibility, and energy efficiency. For evaluation, the MRSA is implemented on field-programmable gate arrays (FPGAs) to examine its actual performance, consumption, and correctness. Evaluation results on a Xilinx system-on-chip (SoC) with the ALVEO U280 Data Center Accelerator Card FPGA show that the MRSA is much more power-efficient than some of the most powerful commercial CPUs, GPUs, and other FPGA implementations. On the ALVEO U280, the MRSA achieves a maximum hash rate of 296.76 kHash/s, a throughput of 304.9 Mbps when reaching a maximum frequency of 259.94 MHz, and a power consumption of 18.12 W. The energy efficiency of the MRSA on the ALVEO U280 SoC is 52.83 and 867.88 times higher than those on an RTX 3090 GPU and an i9-10940X CPU, respectively.

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EMAXVR: A programmable accelerator employing near ALU utilization to DSA

Cited by 4 publications

References 5 publications

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth

MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security

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