Recently, general-purpose processors have made the transition from high-frequency single cores to multiple cores as a consequence of multi-core processors requiring less power. To further reduce power consumption, it is necessary for field-programmable gate arrays (FPGAs) to embed multicore processors. In this paper, we design a multi core processor which processor is embedded into SAFHC cluster. As an electromagnetic simulation by FDTD, we propose a multi-core FPGA execution using ASIP (Application-Specific Instruction Set Processor). In the performance evaluations, we achieved a speed up with two cores of 41% over compared with a single core. The integral power consumption of two cores is 21% lower than that of a single core.
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