Elicitation of Scattering Parameters of Dual-halo Dual-dielectric Triple-material Surrounding Gate (DH-DD-TM-SG) MOSFET for Microwave Frequency Applications

Gupta, Neeraj; Kumar, Prashant

doi:10.15598/aeee.v19i1.3788

Cited by 7 publications

(6 citation statements)

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“…The sub-threshold slope of value 60 mV/decade is considered ideal and the simulated value and computed value of SS closely matches with an ideal value of SS. The sub-threshold slope is 74.3 mV/decade for TM-SG MOSFET [26]. The proposed device exhibits 16.1 % improvement in SS as compared to TM-SG.…”

Section: Resultsmentioning

confidence: 91%

“…Initially, the current flows from source to drain in the z-direction. Therefore, the total current density JC(r,z) is given by [26].…”

Section: Analytical Modelmentioning

confidence: 99%

“…As the SD-TM-CGAA-JLFET is having a symmetrical structure, the equation ( 10) can be simplified as [26] M a ≈ e qΨ a (r,z a min ) K B T + e qΨ a (0,z a min ) K B T (11) Where a=1,2 and 3 for different metals M1, M2 and M3.…”

Section: Analytical Modelmentioning

confidence: 99%

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Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications

Kumar

Vashisht

Gupta

et al. 2021

Preprint

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Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET. The analytical results were compared with TMSG MOSFET and good agreement was obtained. The sub-threshold current of the device is very low and consider for the implementation of CMOS inverter. A PMOS transistor is designed and the drive current of the PMOS transistor is tuned with the NMOS device to obtain the ideal matching in the drive current. A CMOS inverter has been designed. The transient and DC behavior of the device have been examined. The power dissipation of the CMOS inverter has been computed and compared with CMOS DMG-SOI JLT inverter. The power dissipation is 5 times less in proposed device as compared to CMOS DMG-SOI JLT inverter. This exhibits an excellent improvement in power dissipation which is useful for making low power future generation devices.

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Section: Resultsmentioning

confidence: 91%

“…Initially, the current flows from source to drain in the z-direction. Therefore, the total current density JC(r,z) is given by [26].…”

Section: Analytical Modelmentioning

confidence: 99%

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Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications

Kumar

Vashisht

Gupta

et al. 2021

Preprint

Self Cite

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“…Various analytical study of surface potential for junctionless transistor has also been done [6], [7]. It has also been reported that cylindrical surrounding gate MOSFETs shows good switching performance and also can be used for microwave frequency applications [8], [9], [10]. However, the junctionless transistor poses various limitations such as degraded mobilities due to high doping concentrations.…”

Section: Introductionmentioning

confidence: 99%

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Yadav

Rewari

Pandey

2022

Silicon

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In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

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“…It provides higher voltage gain; hence SOI MOSFET device with high-k dielectric can be used for amplification purpose. Thus, it is better option for upcoming SOI MOSFET devices [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Fully Depleted SOI (FD-SOI) MOSFET Incorporating Dielectric Engineering

Kumar

Vashishath

Gupta

et al. 2022

IOP Conf. Ser.: Mater. Sci. Eng.

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This paper presents an efficacy of an FD SOI MOSFET structure in suppressing short channel effects is investigated through 2-Dimenional simulation on ATLAS Silvaco. The electrical comparison between Bulk MOSFET, FD-SOI MOSFET and FD-SOI MOSFET using high-k gate dielectric at 45nm technology has been carried out. The structures have been designed and study of threshold voltage, sub threshold slope, drain current (Ion), leakage current (Ioff), Ion/Ioff, transconductance has been done. The features offered by the new device structure are found to be better than the conventional bulk MOSFET. Aluminum Oxide (Al2O3) has been compared to SiO2 as dielectric material. As the dielectric constant of the materials increased, there is a reduction in the leakage current. It provides higher transconductance and better subthreshold slope, thus resulting in improvement of the device. A comparative analysis has been carried out among bulk MOSFET and SOI MOSFET using aluminum oxide, silicon oxide and silicon nitride as gate dielectric materials. Aluminum Oxide also provides higher drain current as compared to other dielectric materials presented in the paper. Thus, Aluminum Oxide is a good candidate as a dielectric for the future devices as compared to traditional oxides. The proposed device can be useful for low power applications.

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Elicitation of Scattering Parameters of Dual-halo Dual-dielectric Triple-material Surrounding Gate (DH-DD-TM-SG) MOSFET for Microwave Frequency Applications

Cited by 7 publications

References 0 publications

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications

Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Performance Analysis of Fully Depleted SOI (FD-SOI) MOSFET Incorporating Dielectric Engineering

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