Electrostatics of JFET at 6 nm channel length: a simulation study

Abstract

A junction field effect transistor (JFET) is studies as an alternative device for performing complementary logic currently limited to MOS. Complementary logic with cJFET bult using 60 nm lithography was reported recently. This summarises the simulation results of scaled n-channel JFET with a gate length of 6 nm. The JFET was operated in double gate mode. Results of this simulation study reveal that it is possible to scale JFET gate length to 6 nm operating at 0.5 V and achieve an ion/loff ratio greater than 5000. Threshold voltage can be varied by varying the channel profile. In Essence, JFET needs to be considered as a viable candidate for future scaling.Introduction: Research on short channel JFETs to perform logic operations has been reported by multiple sources recently [1-3]. We have reported results of electrical characterisation of n-and p-channel JFETs and results of logic circuits built with a short channel complementary JFET (cJFET) at 90 nm node (Lg ¼ 60 nm) on SOI [1] and on bulk [3]. These circuits were operated at around 0.5 V and shown to be functionally compatible with CMOS. Primary logic circuits such as inverters, NAND/NOR gates and flip-flops designed with a double gate complementary JFET were demonstrated. As a natural extension of the study, we have explored two important aspects of the cJFET; (i) the compatibility of JFET with MOS technology and (ii) the scalability of JFETs. Initial results on both fronts present very encouraging results which are presented here. First, we present the results of the constructing of the SOI-cJFET with CMOS design rules. Using this structure, simulation results of the cJFET scaled to the channel length of 6 nm are presented. The simulation results show that Ion of nearly 100mA, Ion/Ioff ratio of 3-7 × 10 3 for n-channel JFETs operating at 0.5 V and a subthreshold slope of ,90 mV/decade are achievable. A similar Ion/Ioff ratio for a pJFET is expected. These preliminary results suggest that the JFET device is a contender for scaling to sub-10 nm node.Background and structure description: Simulation was performed on JFET transistors constructed on SOI substrate. All these JFETs are operated in double gate mode -the top gate is made of polysilicon which gives this JFET a MOS like appearance, and the bottom gate is formed in the silicon near the bottom interface of the SOI layer, and both gates shorted together for optimum performance [4]. The top gate length is determined by lithography capability and it is commonly used as the scaling parameter. The bottom gate is aligned with the top gate and is larger in dimension, as shown in Fig. 1. Details of fabrication techniques used to build this structure are beyond the scope of this brief report. It suffices to say that it borrows heavily from MOS technology.

CJM: A Compact Model for Double-Gate Junction FETs

“…JFETs are unipolar devices commonly operating in depletion mode (normally-on devices, with a negative threshold for n-JFETs). Ultra-scaled enhancement mode (normally-off), complementary JFETs (cJFETs) using silicon have been proposed for logic applications with channel lengths in the range of 25 nm -10 nm [6]- [8] with gate voltage lower than 0.5 V to prevent a forward-bias of the channel-to-gate junction. For wide-bandgap semiconductors such as silicon carbide (SiC) [9], [10] or gallium nitride (GaN) [11], the gate voltage can be extended beyond 2V due to their high built-in voltage.…”