CJM: A Compact Model for Double-Gate Junction FETs

Abstract

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Furthermore, co-integration of JFET with CMOS technology is attractive. Physicsbased compact models for JFETs are however scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, transconductances and transcapacitances of symmetric DG JFETs, covering all regions of device operation, continuously from subthreshold to linear and saturation operation. This charge-based JFET model (called CJM) constitutes the basis of a full compact model of the DG JFET for analog, RF, and digital circuit simulation.

Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study

“…MOSFETs' scaling down to enhance the device performance and increment the integration density has been pursued for decades [1][2][3]. However, short-channel MOSFETs cannot meet low-power application requirements due to the nonscalable subthreshold slope (SS) at 25 °C.…”

β-Ga2O3 double gate junctionless FET with an efficient volume depletion region

“…The structures like double gate, and Fin MOSFETs improve the short-channeleffects and the Ioff current behavior but difficulty in defining the boundary between the source and drain regions in doping profiles still exists [8]. The junctionless FET (JL-FET) that have no junction at the source-channel and channel-drain interfaces provides a solution to this problem but they show poor high-voltage characteristics [9]- [14][15], [16]- [21][22] [23]. Characteristics of high-voltage breakdown have been investigated in multigate structures [24] [25]and junctionless FETs [26].…”