Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence

Motamedi, Aida; Orouji, Ali A.; Madadi, Dariush

doi:10.1007/s10825-021-01837-x

Cited by 13 publications

(8 citation statements)

References 48 publications

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“…Due to its junction-free construction, it may be made in fewer steps, thermal efficiency, and resistance to SCEs. [1][2][3][4][5][6][7][8] Junctionless transistors have improved subthreshold slope (SS) and drain-induced barrier lowering (DIBL) in contrast to any traditional MOSFET, which has enhanced junctionless device performance.…”

Section: Introductionmentioning

confidence: 99%

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Abrishami

Orouji

2023

Physica Status Solidi (a)

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This work presents a double‐gate junctionless metal‐oxide field‐effect transistor (JLT) in a 20 nm regime by modifying central potential. In the proposed device, the off‐state current is reduced due to modifying the potential in the middle of the channel. The proposed structure is called as a modified central potential junctionless transistor (MCP‐JLT). The suggested device embeds two dielectric pockets (DPs) into the middle of the channel. The proposed technique has several effects on the proposed structure. Also, the impact of the DPs into the channel on the performance device is discussed. The proposed MCP‐JLT structure decreases the off‐state current (IOFF) by three orders of magnitude; besides, it can suppress the lateral electric field and also slightly reduces the drive current (ION), and reduces subthreshold swing (SS) compared to a typical junctionless FET (C‐JLT). Furthermore, the effect of the gate insulator materials on the proposed device's performance is discussed.

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Section: Introductionmentioning

confidence: 99%

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Abrishami

Orouji

2023

Physica Status Solidi (a)

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“…Also, SOI's lower parasitic capacitances and resistances provide good RF and analog Figures of Merits (FoMs). The junctionless FETs (JLFETs) have been suggested as a further effort to solve the SCEs and stringent requirements of an ultra-steep doping characteristic at the metallurgical interfaces as well as complicated heat budgets in standard transistors [10]- [18] The other way to reduce the SCEs is by using the multiple-gate transistors in the scaled MOSFETs [19]- [21]. To improve electrostatic integrity, three modes are combined in this work: SOI, multiple gate FET, and junctionless technology.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Junctionless Fin-FET Characterization in Deep Cryogenic Temperature: DC and RF analysis

Madadi

2022

IEEE Access

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This work presents the SOI Junctionless Fin-FET characterization in Deep Cryogenic behavior (DC-JLFET). Results show that the JLT device is well-suited for various operations, such as computation, sensing, and communication in the quantum field. The cryogenic transfer characteristics, including bias, and interface trap density, are analyzed over a broad temperature range (300 Kelvin down to 4.2 Kelvin). Cryogenic DC and RF analyses were done on the conventional double-gate JL-FET structure, operating at 300 K and below 4.2 K for different geometries. The suggested study illustrates that cryogenic status in the new technology CMOS can be correctly anticipated by calibrating data using an experimental device.

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“…[10][11][12][13][14] To have the complete depletion region structure in the OFF mode, an extremely thin channel or a gate metal with a WF greater than 5.3 eV is required. [15][16][17][18] For these reasons, different methods for obtaining fully depletion regions in JLTs have been investigated. [19][20][21][22][23][24] Regrettably, as the channel size is reduced to the under 20 nm area, getting a complete depletion region becomes a significant roadblock.…”

Section: Introductionmentioning

confidence: 99%

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

Bolokian

Orouji

Abbasi

et al. 2022

Physica Status Solidi (a)

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Herein, the authors suggest a junctionless field effect transistor with an embedded p‐type layer (EPL‐JLT) near the drain channel side, employing calibrated structure simulations to obtain a complete depletion region in a 6 nm channel length. The incorporation of a p‐type layer improves leakage current (I OFF) and subthreshold swing (SS) for a 6 nm regime structure at 5.9 eV work function (WF) while the ON current (I ON) diminishes a little. This considerable achievement in the leakage current enables obtaining multiple threshold voltages (V TH) by adjusting the gate WF. The goal aids in creating optimized structures, which is impossible in silicon JLFETs (Si‐JLT) due to their requirement for large WFs to obtain a depletion region even at higher channel lengths. The proposed device has a leakage current of 1 nA μm−1 even at a 5.1 eV WF. The scaling of the EPL‐JLT for different channel lengths is investigated.

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Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence

Cited by 13 publications

References 48 publications

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

Investigation of Junctionless Fin-FET Characterization in Deep Cryogenic Temperature: DC and RF analysis

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

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