Investigation of Junctionless Fin-FET Characterization in Deep Cryogenic Temperature: DC and RF analysis

Abstract

This work presents the SOI Junctionless Fin-FET characterization in Deep Cryogenic behavior (DC-JLFET). Results show that the JLT device is well-suited for various operations, such as computation, sensing, and communication in the quantum field. The cryogenic transfer characteristics, including bias, and interface trap density, are analyzed over a broad temperature range (300 Kelvin down to 4.2 Kelvin). Cryogenic DC and RF analyses were done on the conventional double-gate JL-FET structure, operating at 300 K and below 4.2 K for different geometries. The suggested study illustrates that cryogenic status in the new technology CMOS can be correctly anticipated by calibrating data using an experimental device.

Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

“…However, gm degrades with increment in VGS indicating reduced carrier mobilities due to increased scattering in the lattice mitigating current. This observable gm oscillation in junction-less devices can accounted for quantum-mechanical conduct [20][21]. The impurity-freezing at DCT results in enhanced carrier mobilities [22] that results in a peak gm = 3.9 mS at 50 K. Fig.…”

“…8 presents the transconductance generation factor profile formulated by gm/ION at DCT. The impact of gm/ION on analog/RF circuitry can be understood by its inverse relation with device SS that denotes circuit power-drain [20]. Therefore, greater the gm/ION less will be the device which means lesser circuit power-drain.…”

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

“…Beyond the excess of off‐state current, the applied gate voltage causes charges to build up close to the surface. [ 16–23 ]…”

“…Beyond the excess of off-state current, the applied gate voltage causes charges to build up close to the surface. [16][17][18][19][20][21][22][23] The body region of the device should remain fully depleted in the junctionless transistor for proper off-state of the device. To achieve this condition, the work function difference between the gate material and substrate must be high enough so that the resulting electric field can maintain the device in a fully depleted condition.…”

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High‐Frequency Application

“…[8] To address these issues, researchers have proposed a disruptive transistor architecture known as the junctionless MOSFET, a revolutionary semiconductor device that has captured the attention of researchers, engineers, and innovators alike. [9,10] With its remarkable simplicity, exceptional performance, and energy efficiency, this cutting-edge transistor is paving the way for a new era in electronics. [11] In traditional MOSFETs, complicated junctions are used to control the flow of current, presenting challenges in manufacturing, power consumption, and performance limitations.…”