β-Ga2O3 double gate junctionless FET with an efficient volume depletion region

Madadi, Dariush; Orouji, Ali A.

doi:10.1016/j.physleta.2021.127575

Cited by 22 publications

(4 citation statements)

References 40 publications

(19 reference statements)

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“…Due to the lack of a path to the substrate side when using Silicon on Insulator (SOI) wafers, several papers investigated to solve MOSFET difficulties such as parasitic capacitance and short channel effects will reduce the thermal conductivity of the structure [11][12][13][14][15][16]. Junctionless FETs (JL-FETs) are extensively doped devices with no difference in active region doping, as a result, the current flow mechanism differs from that of MOSFETs without junctions, and the fabrication procedure will be simple [17][18][19][20][21][22][23][24][25][26][27][28][29][30].…”

Section: Introductionmentioning

confidence: 99%

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

Abrishami,

Orouji,

Madadi

2023

Phys. Scr.

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This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.

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Section: Introductionmentioning

confidence: 99%

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

Abrishami,

Orouji,

Madadi

2023

Phys. Scr.

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“…Multi-gate MOSFETs (MGMOS), as well as gate-all-around (GAA) transistors, are investigated to increase the gate control and the integration density [21]. The double-gate structure consisting of top and back gate also improves the gate controllability like short channel effects [22]. However, there are not many studies on Ga 2 O 3 transistors that investigate the effect of multi-gate including back-gate transistors.…”

Section: Introductionmentioning

confidence: 99%

Improved Properties of Post-Deposition Annealed Ga2O3/SiC and Ga2O3/Al2O3/SiC Back-Gate Transistors Fabricated by Radio Frequency Sputtering

Lee,

Chung

et al. 2023

Micro

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The high breakdown electric field, n-type doping capability, availability of high-quality substrates, and high Baliga’s figure of merit of Ga2O3 demonstrate its potential as a next-generation power semiconductor material. However, the thermal conductivity of Ga2O3 is lower than that of other wide-bandgap materials, resulting in the degradation of the electrical performance and reduced reliability of devices. The heterostructure formation on substrates with high thermal conductivity has been noted to facilitate heat dissipation in devices. In this work, Ga2O3 thin films with an Al2O3 interlayer were deposited on SiC substrates by radio frequency sputtering. Post-deposition annealing was performed at 900 °C for 1 h to crystallize the Ga2O3 thin films. The Auger electron spectroscopy depth profiles revealed the interdiffusion of the Ga and Al atoms at the Ga2O3/Al2O3 interface after annealing. The X-ray diffraction (XRD) results displayed improved crystallinity after annealing and adding the Al2O3 interlayer. The crystallite size increased from 5.72 to 8.09 nm as calculated by the Scherrer equation using the full width at half maximum (FWHM). The carrier mobility was enhanced from 5.31 to 28.39 cm2 V−1 s−1 in the annealed Ga2O3 thin films on Al2O3/SiC. The transfer and output characteristics of the Ga2O3/SiC and Ga2O3/Al2O3/SiC back-gate transistors reflect the trend of the XRD and Hall measurement results. Therefore, this work demonstrated that the physical and electrical properties of the Ga2O3/SiC back-gate transistors can be improved by post-deposition annealing and the introduction of an Al2O3 interlayer.

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“…When the channel is in the ON mode (gate voltage > threshold voltage), the depletion layer thickness will thin, enabling current to flow from the drain side to the source area. [10][11][12][13][14] To have the complete depletion region structure in the OFF mode, an extremely thin channel or a gate metal with a WF greater than 5.3 eV is required. [15][16][17][18] For these reasons, different methods for obtaining fully depletion regions in JLTs have been investigated.…”

Section: Introductionmentioning

confidence: 99%

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

Bolokian

Orouji

Abbasi

et al. 2022

Physica Status Solidi (a)

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Herein, the authors suggest a junctionless field effect transistor with an embedded p‐type layer (EPL‐JLT) near the drain channel side, employing calibrated structure simulations to obtain a complete depletion region in a 6 nm channel length. The incorporation of a p‐type layer improves leakage current (I OFF) and subthreshold swing (SS) for a 6 nm regime structure at 5.9 eV work function (WF) while the ON current (I ON) diminishes a little. This considerable achievement in the leakage current enables obtaining multiple threshold voltages (V TH) by adjusting the gate WF. The goal aids in creating optimized structures, which is impossible in silicon JLFETs (Si‐JLT) due to their requirement for large WFs to obtain a depletion region even at higher channel lengths. The proposed device has a leakage current of 1 nA μm−1 even at a 5.1 eV WF. The scaling of the EPL‐JLT for different channel lengths is investigated.

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β-Ga2O3 double gate junctionless FET with an efficient volume depletion region

Cited by 22 publications

References 40 publications

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

Improved Properties of Post-Deposition Annealed Ga2O3/SiC and Ga2O3/Al2O3/SiC Back-Gate Transistors Fabricated by Radio Frequency Sputtering

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

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