Electrical design and performance of a multichip module on a silicon interposer

Baez, Franklin; Cranmer, Mike; Shapiro, M. J.; Audet, Jean; Berger, D.; Sprogis, E.; Collins, Chris; Iyer, S. S.

doi:10.1109/epeps.2012.6457902

Cited by 10 publications

(4 citation statements)

References 4 publications

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“…The best configuration shows an insertion loss of ≈3 dB at 50 GHz for a 40 mm long line. An insertion loss of 0.5 dB/mm at 4 GHz was measured using differential transmission lines in [5]. The line was used to achieve an 8 Gbps chip-to-chip communication.…”

Section: State Of the Artmentioning

confidence: 99%

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Dittrich

Steinhardt

Heinig

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip in a side-by-side interposer approach. We investigate the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations. The simulations are valued by measurements. Our measurements show that microstrip lines with <0.3 dB/mm insertion loss at 30 GHz can be achieved with a typical polymer based interposer process. In contrast to other work we extend the microstrip line model with pads on both ends to form a complete interconnection. Our investigations show that an insertion loss of <0.55 dB/mm can be achieved assuming dense inter-connections. We investigate the impact of technological variations during the manufacturing process of a silicon interposer. This is important to ensure electrical functionality (signal and power integrity) of the system in mass production. The results on technology variations during the manufacturing process of an interposer show that variations of 20 % in trace width and trace height are changing the characteristic impedance of the line, but do not significantly affect the signal integrity of sufficiently long lines. In contrast, variations of 20 % in polymer height and polymer permittivity in the redistribution layer have more influence on signal integrity of sufficiently long interposer interconnections

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Section: State Of the Artmentioning

confidence: 99%

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Dittrich

Steinhardt

Heinig

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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“…Of course, the lengths of bond wires are limited to about 10 mm and this is suitable for sensors with relatively small total area. For larger sensors one can consider using double metal process on the sensor or employing interposer technology [8], however in such cases the stray capacitance of interconnects becomes predominant in the total input capacitive load.…”

Section: Introductionmentioning

confidence: 99%

Limitations on energy resolution of segmented silicon detectors

et al. 2018

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In the paper experimental study of charge division effects and energy resolution of X-ray silicon pad detectors are presented. The measurements of electrical parameters, capacitances and leakage currents, for six different layouts of pad arrays are reported. The X-ray spectra have been measured using a custom developed dedicated low noise front-end electronics. The spectra measured for six different detector layouts have been analysed in detail with particular emphasis on quantitative evaluation of charge division effects. Main components of the energy resolution due to Fano fluctuations, electronic noise, and charge division, have been estimated for six different sensor layouts. General recommendations regarding optimisation of pad sensor layout for achieving best possible energy resolution have been formulated.

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“…A number of companies are working on TSV interposer technology [1][2][3][4][5][6][7][8][9], and close to 80 million interposer based products are expected to be fabricated in 2014 [10]. Invensas is also developing technology for this growing market.…”

Section: Introductionmentioning

confidence: 99%

TSV module optimization for high performance silicon interposer

Cao¹,

Dinan²,

Sun³

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation. IntroductionEach generation of semiconductor products from cellphones to servers is expected to be faster and more powerful than the previous one. Along with the everexpanding internet and widespread availability of portable devices, more computing power and functionality need to be available in small packages. The number of diverse chips inside these products is increasing rapidly and their integration within a small form factor is driving dense chip packaging technology, such as multi-chip modules (MCM), package on package (POP), package in package (PIP) and 3D integration.2.5D integration using a silicon interposer offers a way to achieve dense chip packaging with high performance interconnects for these applications. The benefits include smaller foot print, lower power consumption, and shorter delays. Silicon interposer can also reduce stress and warpage caused by CTE mismatch between chips and package substrate. Chips built with different process flows, such as logic memory, CMOS image sensor (CIS) and microelectro mechanical systems (MEMS) can be closely connected using the top routing layer of an interposer. Since chips are placed side by side on an interposer, this assembly method reduces the thermal issues of high-power 3D stacked dies.The market for 2.5D technology includes FPGA, ASIC, CPU, GPU, APU, high end memory and mobile applications. A number of companies are working on TSV interposer technology [1][2][3][4][5][6][7][8][9], and close to 80 million interposer based products are expected to be fabricated in 2014 [10]. Invensas is also developing technology for this growing market. There are many technical challenges in TSV interposer manufacturing. This paper describes our interposer test vehicle and our process optimization results.

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Electrical design and performance of a multichip module on a silicon interposer

Cited by 10 publications

References 4 publications

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Limitations on energy resolution of segmented silicon detectors

TSV module optimization for high performance silicon interposer

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